Design Hierarchy

Foundation Express maintains the hierarchical boundaries you define when you use structural Verilog. These boundaries have two major effects.

• Each module you specify in your HDL description is synthesized separately and maintained as a distinct design. The constraints for the design are maintained, and you can optimize each module separately in Foundation Express.
  
  
• The modules that you instantiate within HDL descriptions are maintained during input. The instance name you assign to user-defined components is carried through to the gate-level implementation.
  
  

The “Structural Descriptions” chapter discusses modules and module instantiations.

NOTE

Foundation Express does not automatically maintain (create) the hierarchy of other nonstructural Verilog constructs such as blocks, loops, functions, and tasks. These elements of an HDL description are translated in the context of their design. After analyzing and implementing a design, you can use the Modules constraint table for the implementation to group the gates in a block, function, or task. Refer to the Foundation Express online help for further information.

The choice of hierarchical boundaries has a significant effect on the quality of the synthesized design. You can optimize a design while preserving these hierarchical boundaries using Foundation Express. However, Foundation Express only partially optimizes logic across hierarchical modules. Full optimization is possible across those parts of the design hierarchy that are collapsed in Foundation Express.