Modules

The principal design entity in the Verilog language is a module. A module consists of the module name, its input and output description (port definition), a description of the functionality or implementation for the module (module statements and constructs), and named instantiations. The basic structural parts of a module are illustrated in the following figure.

Figure 3.1 Structural Parts of a Module

The following example shows a simple module that implements a 2-input NAND gate by instantiating an AND gate and an INV gate. The first line of the module definition declares the name of the module and a list of ports. The second and third lines declare the direction for all ports. (Ports are either input, output, or bidirectional.) A wire variable is created in the fourth line of the description.

Next, the two components are instantiated; copies named instance1 and instance2 of the components AND and INV are created. These components are connected to the ports of the module and, finally, connected by using the variable and_out.

    module NAND(a,b,z);    
           input a,b; // Inputs to NAND gate    
           output z; // Outputs from NAND gate    
           wire and_out;// Output from AND gate     
        
           AND instance1(a,b,and_out);    
           INV instance2(and_out, z);    
    endmodule