A port list consists of port expressions that describe the input and output interface for a module. Define the port list in parentheses after the module name, as shown below.
module_name (port_list ) ;
A port expression in a port list can be any of the following.
Concatenation is the process of combining several single-bit or multiple-bit operands into one large bit vector. For more information on concatenation, see the “Expressions” chapter.
Each port in a port list must be declared explicitly as input, output, or bidirectional in the module with an input, output, or inout statement. (See the “Port Declarations” section of this chapter.) For example, the module definition in the module definition example shows that module NAND has three ports, a, b, and z, connected to 1-bit nets a, b, and z. These connections are declared in the input and output statements.
