Introduction

This chapter guides you through a typical field-programmable gate array (FPGA) and complex programmable logic device (CPLD) design procedure from schematic entry to completion of a functioning device. It uses a design called Calc, a 4-bit processor with a stack. In the first part of the tutorial, you use the Design Architect, the Mentor Graphics design entry tool, to create the schematics and symbols for the Calc design. Next you use pld_quicksim, the Mentor Graphics simulator, to perform a functional simulation on it. In the third step, you use the Xilinx Design Manager to implement the design. Finally, you verify the design's timing by again using pld_quicksim. The simple design example used in this tutorial demonstrates many system features that you can apply to more complex FPGA and CPLD designs.

NOTE

Although this tutorial describes creating and processing FPGA designs, you can apply most of the steps to CPLD designs.

This tutorial includes instructions on the following:

• Installing the tutorial files
  
  
• Using Mentor Graphics Design Manager
  
  
• Targeting the tutorial design (Calc) for an XC4000E or an XC9000 device
  
  
• Using Design Architect
  
  
• Completing the ALU block in the Calc design
  
  
• Adding the STARTUP block to tie signals to the global reset
  
  
• Adding device information in the Calc design
  
  
• Exploring Xilinx library elements
  
  
• Exploring the XC4000E oscillator
  
  
• Controlling device layout from the schematic
  
  
• Editing the Calc design for a non-XC4000E/EX device
  
  
• Performing functional simulation on the Calc design in pld_quicksim
  
  
• Converting the design to an EDIF file using pld_men2edif
  
  
• Implementing the design using pld_dsgnmgr
  
  
• Configuring the Xilinx Design Manager/Flow Engine
  
  
• Performing timing simulation on the routed Calc design in pld_quicksim
  
  
• Examining routed designs with the Editor for Programmable ICs (EPIC)
  
  
• Verifying the Calc design on a demonstration board
  
  
• Making incremental design changes
  
  
• Command summaries