Making Incremental Design Changes

After initially placing and routing a design, it is often necessary to go back to the schematic and make slight modifications to the original design. When this situation occurs, much of the place and route information from the previous design iteration can be “recycled,” since much of it is unchanged. This process is known as incremental design, and the NCD file (containing partition, placement, and routing information) from the prior place and route run is used as a guide.

Since much of the place and route information is extracted from the guide file, the place and route time is greatly reduced. The reuse of place and route information also results in more stable timing over a number of guided place and route iterations. Once a section of your design passes your timing requirements, guided design ensures that it passes in the future, even if other parts of the design are modified.

In this section of the tutorial, you make a small change to the schematic and reprocess the design using the guide options available in the Xilinx Flow Engine.

NOTE

A small design change is the addition, removal, or replacement of only a small amount of logic in the design; the exact amount is dependent on the size of the design. If radical changes are made to a design, especially to existing portions of the design, it can be disadvantageous to guide the design.

Making an Incremental Schematic Change

Make a simple change to the Calc schematic that is visible immediately on the demonstration board. For example, assume that the reset opcode is no longer needed and needs to be removed from the design. This can be done by grounding the `R' pins that are inputs to the FDRE and FD4RE macros in the ALU schematic. The logic that generated the original reset signal, and the logic it drove, is automatically optimized out of the netlist by the MAP program.

Open pld_da and load the Calc schematic as follows.

1. From pld_dmgr, select the $XILINX_TUTORIAL/calc_sch/alu design object and choose Right Mouse Button Open pld_da.
   
   Design Architect appears with the ALU schematic loaded.
   
   
2. Use the F8 key, or the stroke 159, to zoom in on the lower right quadrant of the schematic.
   
   
3. Press the F2 key to make sure nothing is selected.
   
   
4. Select the AND5B2 component that generates the QRESET net feeding the FDRE and FD4RE.
   
   
5. Press the Delete key to delete the component.
   
   
6. Connect a ground symbol to the dangling QRESET net.
   
   The GND symbol can be found in the BY TYPE general section of the Xilinx Library menu. See the figure below.
   
   
7. Check and save the schematic.
   
   
8. Exit pld_da and return to pld_dmgr.
   
   

   Figure 9.82 Grounding the Reset Logic

Translating the Incremental Design

Translate the guided Calc design by turning on the guide options in Flow Engine. The following instructions demonstrate an alternative method of running Flow Engine that offers more control over the implementation flow.

1. In the Xilinx Design Manager, select calc, then choose Design New Version.
   
   
2. The New Version dialog box appears with the Name field automatically filled in as ver2. You may also add a comment to the new version. This comment appears in the project view next to the version number. Click OK.
   
   

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   NOTE

   You can add a comment to any version or revision in the project view by selecting that version or revision, then selecting Right Mouse Button Properties.

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3. Select the newly created ver2 in the project view, then select Design New Revision.
   
   The New Revision dialog box appears with the Name field automatically filled in as rev1 and the Part field automatically filled in as XC4003E-4-PC84. You may add a comment to the new revision if you wish.
   
   
4. Click OK to close the dialog box.
   
   
5. Select the newly created “rev1” in the project view, then select Tools Flow Engine. Alternatively, you can click the Flow Engine icon in the Toolbox.
   
   

   Figure 9.83 Flow Engine Icon

   Flow Engine appears. However, unlike the procedure you used in the first revision, the implementation flow does not start automatically. This allows you to step forward and even backward through the implementation flow by individual stages, using the audio-player-like buttons at the bottom of the Flow Engine window, or the selections underneath the Flow menu.
   
   
6. Select Setup Options from the menu bar.
   
   The Options dialog box appears as before.
   
   
7. Go through the different options as before and verify that the settings you gave in the previous revision have been carried over into this revision.
   
   
8. In the Guide Design field, select Last.
   
   This sets the previous revision of the placed and routed design. In this case, it has the same effect as selecting ver1 rev1.
   
   
9. Click OK to return to Flow Engine.
   
   
10. Run the implementation as before by clicking the play button (on the far left) at the bottom on the Flow Engine window.
    
    
11. When all steps have completed successfully, select Flow Close to exit Flow Engine.
    
    

Verifying the Change in the Demonstration Board

Verify that the change was performed by downloading the new bitstream to the demonstration board, as you did previously. As before, see the “CALC Tutorial” section of the Hardware Debugger Reference/User Guide for more information. Before running through this tutorial, make sure that the ver2 rev1 revision is selected in the project view.