The XC4000E/L/EX/XL/XLA/XV and XC5200 DesignWare libraries describe adders, subtracters, comparators, incrementers, and decrementers that map to the fast carry logic structures available in the target architecture.
For XC4000E/L/EX/XL/XLA/XV and XC5200 designs using VHDL or Verilog arithmetic operators, take advantage of the Xilinx DesignWare (XDW) library. This library contains the arithmetic functions that utilize the XC4000E/L/EX/XL/XLA/XV and XC5200 dedicated carry logic to improve both the area and speed of the design.
The following table lists the VHDL and Verilog arithmetic operators and the XDW modules to which they map.
| Operators | XDW Module |
|---|---|
| + | ADD_SUB |
| - | ADD_SUB |
| <, <=, >, >= | COMPARE |
| + 1 | INC_DEC |
| - 1 | INC_DEC |
The XDW library contains twos complement and unsigned binary modules of widths 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, and 48. Additionally, you can use available 64-bit widths for the COMPARE module only. Operands falling between bit ranges map to the next higher bit-width module. The Xilinx design implementation tools remove any unused logic when implementing a smaller bit width or when adding, subtracting, or comparing with a constant value.
The XDW library contains area and speed information for its modules. This information allows FPGA Compiler and Design Compiler to compare XDW implementations of arithmetic functions to other DesignWare libraries available at compile time. XSI then selects the implementation that best meets your timing and area constraints.
XC4000E/L/EX/XL/XLA/XV devices accommodate two bits of arithmetic function per CLB, and XC5200 devices accommodate four bits per CLB. XC4000E/L/EX/XL/XLA/XV devices implement arithmetic functions in one vertical column of CLBs. The carry propagation direction is upward in XC4000EX/XL/XLA/XV devices and up or down in XC4000E/L devices. XC5200 devices implement arithmetic functions in two vertical columns of CLBs and have an upward carry propagation direction.
The Xilinx place and route tools determine the best placement for the CLB columns in the target device and break or wrap a column if constrained by the physical boundaries of the device. However, as a general rule, choose a target device that can accommodate the “tallest” arithmetic structure in your design without altering the shape of this structure. Selecting the correct device makes it easier to place and route predominately data path-based designs.
