This section describes the programs you use when translating, mapping, placing, and routing your design using the XSI and Synopsys tools. You can use the following programs with both Design Compiler and FPGA Compiler.
| Program | Description |
|---|---|
| Design Analyzer | Design Analyzer is the Synopsys graphic interface to the Synopsys synthesis tools. |
| DC Shell | DC Shell is the Synopsys UNIX command-line interface for entering commands, arguments, and options to the Synopsys synthesis tools. |
| Synlibs | This program displays the target and link libraries for the specified part type and speed grade. You can append the output of the Synlibs command to the .synopsys_dc.setup file. NOTE: You must list the libraries in your setup file in the order that they appear in the Synlibs output. |
| VHDLAN | The VHDLAN program analyzes a VHD source file for simulation. Use the -i option with this program. |
| VHDLDBX | The VHDLDBX program is the VHDL Debugger, a graphic interface to the VHDL simulator. Through its dialog box, you can issue simulator commands, view command output, and view source code. |
| NGDBUILD | This program reads a netlist file in XNF or EDIF format and creates an NGD file describing a logical design. |
| DC2NCF | This program translates a Synopsys DC file to a netlist constraints file (NCF) file. The DC file is a Synopsys file containing your design constraints. |
| MAP | This program maps a logical design to a Xilinx FPGA. |
| TRACE | This program provides static timing analysis of your design based on input timing constraints. |
| PAR | This program takes an NCD file, places and routes the design, and outputs an NCD file, which is then used by the BitGen program. |
| NGDAnno | This program distributes delays, setup and hold times, and pulse widths found in the physical NCD design file back to the logical NGD file. |
| NGD2VHDL or NGD2VER | These programs convert Xilinx NGD format into structural HDL for gate-level simulation. Netlist consists of SimPrims. |
| BitGen | This program produces a bitstream for Xilinx device configuration. It takes a fully routed NCD file as its input and creates a configuration bitstream. |
