Updated tutorials are available after June 30, 1998 from the Xilinx Web site and on the AppLINX CD. The Web site location is (http://www.xilinx.com/support/techsup/tutorials). Please contact your local Sales Representative for a copy of the AppLINX CD.
This tutorial guides you through the FPGA design process. The steps in this process include HDL design entry, design implementation, design simulation, and downloading the design to a functioning device.
The design used in this tutorial is called Calc, a 4-bit processor with a stack. The simple design example used in this tutorial demonstrates many system features that you can apply to more complex FPGA designs. This tutorial assumes that you have a working knowledge of the Synopsys FPGA Compiler and the Design Compiler.
For a Verilog version of this tutorial (which uses Verilog-XL as a simulator), refer to the Synopsys FPGA Compiler Expert Journal at (http://www.xilinx.com/support/techsup/journals/index.htm).
This chapter includes the following sections.
