The following kinds of operands can be used in an expression.
Each of these operands is explained in the following subsections.
A number is either a constant value or a value specified as a parameter. The expression size-1 in the example from the “Constant-Valued Expressions” section illustrates how you can use both a parameter and a constant in an expression.
You can define constants as sized or unsized, in binary, octal, decimal, or hexadecimal bases. The default size of an unsized constant is 32 bits. Refer to the “Verilog Syntax” chapter for a discussion of the format for numbers.
Variables that represent both wires and registers are allowed in an expression. (Wires are described in the “Structural Descriptions” chapter. Registers are described in the “Functional Descriptions” chapter.) If the variable is a multibit vector and you use only the name of the variable, the entire vector is used in the expression. You can use bit-selects and part-selects to select single or multiple bits, respectively, from a vector. These are described in the next two sections.
In the Verilog fragment shown in the following example, a, b, and c are 8-bit vectors of wires. Because only the variable names appear in the expression, the entire vector of each wire is used in evaluating the expression.
wire [7:0] a,b,c;
assign c=a & b; A bit-select is the selection of a single bit from a wire, register, or parameter vector. The value of the expression in brackets ( [ ] ) selects the bit you want from the vector. The selected bit must be within the declared range of the vector. The following simple example shows a bit-select with an expression.
wire [7:0] a,b,c;
assign c[0]=a[0] & b[0];A part-select is the selection of a group of bits from a wire, register, or parameter vector. The part-select expression must be constant-valued in the Verilog language, unlike the bit-select operator. If a variable is declared with ascending indices or descending indices, the part-select (when applied to that variable) must be in the same order.
The expression in the example of the wire operands (in the “Wires and Registers” section of this chapter) can also be written (with descending indices) as shown in the example below.
assign c[7:0]=a[7:0] & b[7:0]
In Verilog, you can call one function from inside an expression and use the return value from the called function as an operand. Functions in Verilog return a value consisting of one or more bits. The syntax of a function call is the function name followed by a comma-separated list of function inputs enclosed in parentheses. The following example shows the function call 'legal' used in an expression.
assign error=!legal(in1,in2);
Functions are described in the “Functional Descriptions” chapter.
Concatenation is the process of combining several single-bit or multiple-bit operands into one large bit vector. The use of the concatenation operators, a pair of braces ({ }), is described in the “Concatenation Operator” section of this chapter.
The following example shows two 4-bit vectors (nibble1 and nibble2) that are joined to form an 8-bit vector that is assigned to an 8-bit wire vector (byte).
wire [7:0] byte;
wire [3:0] nibble1, nibble2;
assign byte={nibble1,nibble2};