Building an Always Block

The third step to translating a flip-flop is to build an always block that replaces the flip-flop instantiations - the three statements that begin with dFF as in the example below.

      dFF a_reg ( new_a, clk, a );
      dFF b_reg ( new_b, clk, b );
      dFF c_reg ( new_c, clk, c );

1. Use the clock signal, clk, as the event-expression of the new always block, as shown in the following example.
   
   always @ ( posedge clk ) begin
   
   
2. Put the values and the registers in the body of the always block.
   
   The Q output values in the old module (a, b, and c) become the assigned values in the new version. The clock from the old version is specified in the event-expression of the new always block. The D input values in the old module (new_a, new_b, and new_c) become the values read by the new version, as shown in the example below.
   
   always @ ( posedge clk ) begin
a = new_a ;
b = new_b ;
c = new_c ;
end
   
   
3. Label the input and output signals in the module.
   
   Look at the variable declarations and determine which of the wires and functions serve the flip-flop and which serve the logic of the module.
   
   In the following example, as in most cases, the module's inputs and outputs remain the same. However, you must change the wire values to reg values.
   
   module simple ( d, e, f, load, clk, zero );
input d, e, f, load, clk;
output zero;
reg new_a, new_b, new_c;
   
   
4. Declare the output zero twice; once as the output and once as a reg, so it can be used in the always block.
   
   
5. Make the former function variables a, b, and c into reg variables, because they are now assigned within the second always block as shown in the example below.
   
   module new_simple ( d, e, f, load, clk, zero );
input d, e, f, load, clk;
output zero;
reg zero;
reg a, b, c;
reg new_a, new_b, new_c;
   
   

The following example shows the complete new module with always blocks.

   module new_simple ( d, e, f, load, clk, zero );
      input d, e, f, load, clk;
      output zero; 
      reg zero;
      reg a, b, c;
      reg new_a, new_b, new_c;
   

   always @ ( a or b or c or d or e or f or load ) begin
      if ( load ) begin
      new_a = d;
      new_b = e;
      new_c = f;
      end
      else begin
      new_a = a;
      new_b = b;
      new_c = c;
      end
   

      if ( a==0 & b==0 & c==0 )
      zero=1;
      else
      zero=0;
   end
   

   always @ ( posedge clk ) begin
      a = new_a ;
      b = new_b ;
      c = new_c ;
   end
   endmodule