Determining the Module Description Parts

Once you understand the function of the module, determine what parts of the module description provide the flip-flop behavior. The following example shows a simple module that uses three manually inserted flip-flops.

   module simple ( d, e, f, load, clk, zero );
      input d, e, f, load, clk;
      output zero;
      reg new_a, new_b, new_c;
   

   function zilch ;
      input load, a, b, c
   

   begin 
      if ( load ) begin
         new_a = d;
         new_b = e;
         new_c = f;
      end
      else begin 
         new_a = a;
         new_b = b;
         new_c = c;
      end
   

      if ( a==0 & b==0 & c==0 )
         zilch=1;
      else
         zilch=0;
      end
   

   endfunction

   FD1S a_reg ( new_a, clk, a, );
   FD1S b_reg ( new_b, clk, b, );
   FD1S c_reg ( new_c, clk, c, );
   

   assign zero = zilch ( load, a, b, c );
   endmodule

This module evaluates the three state variables, a, b, and c, to determine whether all the values are 0. Additional input signals are load, which forces a synchronous reset, and clk, which is the module's clock. The functionality of the module is described in the function zilch. The input values are latched in the flip-flop described in the three statements beginning with dFF (a D-type edge-triggered flip-flop). A final assign statement assigns the returned value of the function zilch to the output zero.

The above example generates the schematic shown in the figure below.

Figure 8.1 Schematic of Existing Module

To translate this description, find the combinatorial logic and determine the triggering events. In the following example, the function zilch creates combinatorial logic.

      function zilch ;
      input load, a, b, c;
   

   if ( load ) begin
      new_a = d;
      new_b = e;
      new_c = f;
   end
   else begin 
      new_a = a;
      new_b = b;
      new_c = c;
   end
   if ( a==0 & b==0 & c==0 )
      zilch=1;
   else
      zilch=0;
   endfunction 

In the above example, the values of a, b, c, d, e, f, and load are the triggers (signals that are read). You can rewrite this description as an always block with triggers, as shown in the following example.

   always @ ( a or b or c or d or e or f or load ) begin
   if ( load ) begin
      new_a = d
      new_b = e;
      new_c = f;
   end
   else begin
      new_a = a;
      new_b = b;
      new_c = c;
   end
   

   if ( a==0 & b==0 & c==0 )
      zero=1;
   else
      zero=0;
   end