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Miscellaneous Constructs

The Verilog ifdef, else, and endif preprocessor directives are new in Foundation Express.

The following two examples show the new Verilog directives.

`define def1 /* comment out this `define to get module IFDEF_OR  */
                   /* do not comment out to get module IFDEF_AND */
`ifdef def1
     module IFDEF_AND (a,b,z);
      inputa;
      inputb;
      output;
        assign = a && b;
     endmodule
`else
     module IFDEF_OR (a,b,z);
      input a;
      input b;
      output z;
        assign z = || b;
     endmodule
`endif
`define def2    /* comment out this `define to get b && a */
                   /* do not comment out to get b || a */
module IFDEF_FF(out,a,b,clk);     //verilog file IFDEF_FF.v
    output out;
    input clk,a,b;
    reg out;
   
    always@(posedge clk)
     begin
      `ifdef def2
         out = b && a;
      `else 
         out = b || a;
      `endif
     end
endmodule

Simulation Directives

Simulation directives (not to be confused with Foundation Express directives described in the “Foundation Express Compiler Directives” chapter) refer to special commands that affect the operation of the Verilog HDL Simulator. You can include these directives in your design description, because Foundation Express parses and ignores them.

`accelerate
`celldefine
`default_nettype
`endcelldefine
`endprotect
`expand_vectornets
`noaccelerate
`noexpand_vectornets
`noremove_netnames
`nounconnected_drive
`protect
`remove_netnames
`resetall`timescale
`unconnected_drive

Verilog System Functions

Verilog system functions are implemented by the Verilog HDL simulators to generate input or output during simulation. Their names start with a dollar sign ($). Foundation Express parses and ignores Verilog system functions.

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