This chapter guides you through a typical field-programmable gate array (FPGA) and complex programmable logic device (CPLD) design procedure from schematic entry with instantiated HDL to completion of a functioning device. It uses a design called Calc, a 4-bit processor with a stack. In the first part of the tutorial, you use the Design Architect, the Mentor Graphics design entry tool, to link HDL entities to Mentor symbols and instantiate those symbols into the Calc design. Next, you use QuickHDL Pro, the Mentor Graphics schematic/HDL simulator, to perform a functional simulation on it. In the third step, you use the Xilinx Design Manager to implement the design. Finally, you verify the design's timing by using pld_quicksim. The simple design example used in this tutorial demonstrates many system features that you can apply to more complex FPGA and CPLD designs.
Although this tutorial describes creating and processing FPGA designs, you can apply most of the steps to CPLD designs. Unlike the “Schematic Design Tutorial” chapter, this tutorial focuses completely on FPGAs. For information on retargeting a design to a different device family, see the “Targeting the Design for the XC9000 Family” section of the “Schematic Design Tutorial” chapterUnlike the.
This tutorial includes instructions on the following:
