Chapter 10

Schematic-on-Top with VHDL Tutorial

NOTE

Updated tutorials will be available after June 30, 1998 from the Xilinx Web site and on the AppLINX CD. The Web site location is (http://www.xilinx.com/support/techsup/tutorials). Please contact your local Sales Representative for a copy of the AppLINX CD.

This chapter contains the following sections:

• “Introduction”
  
  
• “Required Background Knowledge”
  
  
• “Design Flow”
  
  
• “Software Installation”
  
  
• “Starting the Design Manager”
  
  
• “Copying the Tutorial Files”
  
  
• “Starting Design Architect”
  
  
• “Completing the Calc Design”
  
  
• “Using a Constraints File”
  
  
• “Performing Functional Simulation”
  
  
• “Using Pld_men2edif”
  
  
• “Using the Xilinx Design Manager”
  
  
• “Performing Timing Simulation”
  
  
• “Examining Routed Designs with EPIC”
  
  
• “Verifying the Design Using a Demonstration Board”
  
  
• “Command Summaries”
  
  
• “Further Reading”