See the “Design Flows” section of the “Introduction” chapter for the design flow involved in using the Mentor Graphics interface. That chapter also describes the general steps for creating a top-level schematic design with instantiated VHDL modules using the Mentor interface.
To instantiate Verilog modules into a schematic in Design Architect, you must first encapsulate them within a VHDL entity. You then encapsulate the VHDL entity into the schematic.
The tutorial design is targeted for an XC4000E device. You can use a Xilinx demonstration board to test the functionality of your design. Make sure your demonstration board and software support your selected device. To determine compatibility, refer to the release notes that came with your software package.
