Design Flows

You use different PLD design flows for performing design entry, implementation and simulation depending on whether you use schematic design entry or HDL design entry.

In either case, the easiest and most automatic way is to use the application icons in the Design Manager window. You can also run the various programs in the design flow manually from the UNIX shell. The shell commands are described in the “Manual Translation” chapter.

The Mentor interface supports the following design flows:

Schematic entry with the Unified Libraries components, LogiBLOX symbols, or both
Schematic entry with Unified Library components with some models expressed in Xilinx compliant EDIF or XNF
Top-down HDL (Verilog/VHDL) design entry and synthesis
Mixed schematic and VHDL design with VHDL on top
Mixed schematic and VHDL design with schematic on top

Schematic Entry Design Flows

The schematic entry design flows are illustrated in the following three figures:

Figure 1.2 Schematic Design Entry Including EDIF-Based and LogiBLOX Modules

Figure 1.3 Design Entry with XNF Top-Level Module

Figure 1.4 Schematic Design Entry with XNF Module

HDL Entry

The following figure shows the design flow for VHDL and Verilog design entry and synthesis for all supported technologies.

Figure 1.5 HDL (Verilog/VHDL) Design Entry and Synthesis

Mixed Schematic and VHDL Flow with VHDL on Top

The design flow for design entry of a top-level VHDL design with a schematic sub-module embedded within is illustrated in the following figure.

Figure 1.6 Mixed Schematic and VHDL Design with VHDL on Top

Mixed Schematic and VHDL Flow with Schematic on Top

The design flow for design entry using a mixture of schematics, VHDL, and Verilog is illustrated in the following figure.