The following sections describe the major features available in this release.
This interface supports the Mentor C.1 software release.
This release offers a number of features that allow you to process a design through a VHDL or Verilog netlist.
This release supports the ModelSim™ simulator, which simulates behavioral VHDL, Verilog, VHDL-based, and Verilog-based gate-level designs composed of SIMPRIM elements. In addition, LogiBlox elements can be simulated at the behavioral level.
It also supports QuickHDL PRO™ for mixed mode simulations for schematic-based and VHDL-based designs. QuickHDL PRO can invoke ModelSim to simulate VHDL-based elements, or quicksim to simulate Unified Libraries elements.
This documentation assumes that you are using ModelSim. However, QuickHDL provides the same functionality as ModelSim. If you are using QuickHDL instead of ModelSim, see the “ModelSim and QuickHDL” appendix for details on how to use QuickHDL in place of ModelSim.
This release supports VHDL simulation, including IEEE-standard 1076.4 VHDL libraries of SIMPRIM models. Xilinx implementation tools output timing simulation VHDL netlists by using structural VHDL models of SIMPRIM VHDL models and an SDF file.
This release supports Verilog simulation, including Verilog libraries for use with SIMPRIM models. Xilinx implementation tools output timing Verilog netlists by using structural Verilog models with SIMPRIM Verilog models and an SDF file.
The Mentor interface can accept Synopsys synthesized netlists in the form of SEDIF or SXNF files. It can also accept XNF and EDIF files from other synthesizers that are compatible with the Xilinx implementation software. These files can be directly submitted to the Xilinx Design Manager for placement and routing of the design.
You can also simulate these EDIF or SXNF files by submitting them to the pld_edif2sim or pld_xnf2sim utility, which creates EDDM components for use with pld_quicksim.
In addition, after place and route, you can output VHDL and Verilog netlists, which can be submitted to ModelSim for simulation with SDF files providing the back-annotation information.
The Mentor Graphics Design Manager is an easy-to-use interface that represents applications and design files as icons. You can now perform many tasks in the Design Manager window that were previously done at the operating system level. The Design Manager runs in a window on your workstation display and makes it easy for you to invoke applications and to manage designs, files, and directories. The Design Manager lets you do these tasks by using graphical point-and-click actions. You can run applications by selecting an application icon, or a design object icon and a menu item.
A design object consists of the files and directories that make up your design.
The Xilinx script, pld_dmgr, configures the Design Manager for the creation, implementation, and simulation of Xilinx designs. This manual describes only the Xilinx-configured Design Manager; refer to Mentor Graphics documentation for a more comprehensive description of the Mentor Design Manager.
The Design Manager includes a Tools window, a Navigator window, and a Design Manager palette, as shown in the following figure:
Figure 1.1 Mentor Design Manager Window |  |
The Tools window contains icons representing all the Mentor Graphics and Xilinx applications that you need to execute the steps in the design flow. The Navigator window contains design object icons, including original schematics as well as files created during translation and simulation. This window makes it easy to access files in different directories. The Design Manager palette provides easy access to the most commonly used Design Manager menu items.
The remainder of this section briefly describes the icons in the Tools window and the Mentor programs they represent. The tools with names that begin with PLD are configured through scripts for working with Xilinx designs.
Pld_da is Mentor's Design Architect®, a schematic editor configured for Xilinx designs. The Xilinx-configured Design Architect is identical to the Mentor Graphics version except for the addition of a Xilinx library of primitives, macros, and utilities such as Convert Design. Refer to the “Design Entry” section of the “Schematic Designs” chapter in this manual and the “Schematic Design Tutorial” chapter in this Manual for more information on creating Xilinx designs with Design Architect. For a more detailed description of Design Architect commands and processes, refer to the Mentor Graphics Design Architect User's Manual.
Pld_dve is the Mentor Graphics Design Viewpoint Editor (DVE) configured for Xilinx designs. When you invoke this application from within the Mentor Design Manager, a dialog box appears and you are asked to create either a simulation or custom viewpoint. Refer to the “Functional Simulation” section of the “Schematic Designs” chapter and the “Timing Simulation for Schematic Designs” section of the “Schematic Designs” chapter in this manual for more information on pld_dve. For detailed information on DVE, refer to the Mentor Graphics Design Viewpoint Editor User's and Reference Manual.
Pld_quicksim is an interactive logic simulator that performs functional or timing simulation on your designs. For more information on pld_quicksim, refer to the “Functional Simulation” section of the “Schematic Designs” chapter, the “Timing Simulation for Schematic Designs” section of the “Schematic Designs” chapter, and the “Schematic Design Tutorial” chapter in this manual. For a detailed description of pld_quicksim, refer to the Mentor Graphics QuickSim II User's Manual.
The Editor icon represents the Mentor Graphics Notepad editor. Notepad is a full-featured, window-based text editor. For more information on Notepad, refer to the Mentor Graphics Notepad User's and Reference Manual.
QuickPath™ performs static and slack timing analysis on designs. For more information on QuickPath, refer to the “Timing Simulation for Schematic Designs” section of the “Schematic Designs” chapter and the “Schematic Design Tutorial” chapter in this manual. For a detailed description of QuickPath, refer to the Mentor Graphics QuickPath User's and Reference Manual.
This is a stand-alone Xilinx tool for generating VHDL and Verilog models of LogiBlox components. Schematic models can be created by invoking LogiBLOX from within pld_da under the Xilinx Libraries Palette menu.
Gen_Arch creates a VHDL architecture from a Mentor schematic (EDDM) component for use in mixed schematic and HDL simulations within QuickHDL Pro.
SysArch is the System Architect™, which creates system-level designs and outputs synthesizable VHDL.
Pld_edif2sim is a utility that converts a Mentor, Synopsys, or other Xilinx compatible EDIF file into a Mentor EDDM single-object simulation model, VHDL netlist, or Verilog netlist. Pld_edif2sim is for functional simulation only.
Pld_edif2tim is the Mentor EDIF netlist reader, which converts a placed and routed EDIF netlist to a Mentor single-object EDDM file that can be submitted to pld_quicksim for timing simulation.
Pld_xnf2sim is a utility that converts an unrouted XNF file to a Mentor EDDM single-object simulation model. This conversion can only be done on chip-level XNF files with EXT records, not on lower level modules embedded in a schematic. VHDL or Verilog simulation models can also be generated. Pld_xnf2sim is for functional simulation only.
Pld_men2edif converts a Mentor schematic to a hierarchical EDIF netlist that is ready for implementation.
ModelSim™ (vsim) is Mentor's simulator for behavioral VHDL, Verilog, or VHDL-based and Verilog-based gate-level designs composed of SIMPRIM elements.
QuickHDL PRO™ (qhpro) is Mentor's simulator for mixed schematic-based, VHDL-based, and Verilog-based designs. It can invoke ModelSim to simulate HDL-based elements, or pld_quicksim to simulate Unified Schematic Library elements.
The Mentor Design Manager interface contains a Pld_dsgnmgr icon for the Xilinx Design Manager. Pld_dsgnmgr is the Xilinx Design Manager, which implements the design. You can access any individual Xilinx tool from the Xilinx Design Manager.
Pld_sg is the Mentor schematic generator (SG), which creates a schematic from an EDDM single object netlist. You can use this tool to generate a schematic for the timing simulation netlist.
You can enter a schematic using LogiBLOX symbols along with other Unified Libraries elements. For schematics, invoke LogiBLOX from within pld_da by using the Xilinx Libraries menu (Libraries 
Xilinx Libraries Logiblox). In addition, EDDM simulation models are automatically created for LogiBLOX symbols during symbol creation.
For VHDL or Verilog LogiBlox models, invoke LogiBlox from the pld_dmgr's tool window, or from the popup session window within pld_da.
This release supports EDIF 2 0 0 for design implementation. Refer to the Xilinx EDIF specification for supported constructs.
Cross-probing is a way of cross-referencing between the original schematic and the timing simulation model after placement and routing. Once a Mentor design is translated, expanded, mapped, placed, and routed, you can extract the back-annotation information and create a hierarchical EDIF netlist. After you convert this EDIF to an EDDM model using pld_edif2tim, you submit it to pld_dve to create a viewpoint and then to pld_quicksim for timing simulation. The resulting data base preserves the design hierarchy, and although it is created in terms of the SIMPRIM library, most of the original net names are still available. You enable cross-probing by invoking QuickSim with the -cp option. This option invokes pld_dve as well as pld_quicksim. You then open the original design viewpoint in pld_dve and view the desired design sheet. If you display the original schematic in pld_dve, you can select nets on the original schematic and view them in the QuickSim trace window.
For more details on cross-probing, see the following sections:
This release supports back-annotated timing simulation after placement and routing. Pld_edif2tim translates the routed EDIF file to an EDDM single-object netlist.
The schematic generator is a utility that you can optionally use to generate a hierarchical schematic from a back-annotated EDDM model. This is not a required step since you can instead use cross-probing with the back-annotated EDDM model and the original schematic for simulation without generating a back-annotated schematic. You can invoke the schematic generator from within the design manager or from a shell by typing pld_sg. You must have a Mentor schematic generator license in order to use this tool.
You can add timing constraints to the schematic as properties. You can also place them in a UCF (user constraints file) that NGDBuild can process. If a conflict arises between the timing information in the EDIF file and in the constraints file, the information in the constraints file prevails.
