Functional Simulation

Functional simulation provides an effective means of identifying logic errors in your design before it is implemented in a Xilinx device. Since timing information for the design is not available, the simulator tests the logic in the design using unit delays. Finding errors before routing your design saves debugging time later in the design process.

You can functionally simulate XNF or EDIF based designs by using pld_xnf2sim or pld_edif2sim to convert the designs to a Mentor simulation model. The EDIF design must be Xilinx compatible and expressed in Unified Library components. The following figure illustrates the design flow for these types of designs.

Figure 3.9 Functional Simulation Flow Diagram

The “Performing Functional Simulation” section of the “Schematic Design Tutorial” chapter in this manual provides a detailed example of the steps involved in functional simulation.

Simulating Pure Schematic Designs

This section describes how to simulate purely schematic designs - designs that are composed solely of elements from the Unified Libraries and that have been entered through Design Architect. Performing functional simulation on a pure schematic design consists of creating a viewpoint in pld_dve from the schematic that you created in Design Architect and using pld_quicksim to simulate the design.

Creating the Viewpoint

After creating a schematic design with Design Architect and a Xilinx library, the next step in the functional simulation flow is to configure a viewpoint for the simulator. Without a correct simulation viewpoint, you will not be able to simulate your design. The viewpoint defines primitives and parameters for design evaluation and analysis.

Pld_dve invokes the Mentor Graphics Design Viewpoint Editor (DVE) to configure a viewpoint for Xilinx designs.

Create the viewpoint for the top-level component that was created in Design Architect.

To invoke DVE, double-click the left mouse button on the pld_dve icon in the Design Manager Tools window.

Alternatively, you can select the top-level component in the Navigator window and click the right mouse button to invoke pld_dve.

The dialog box shown in the “Pld_dve Dialog Box” figure appears. For a more detailed description of DVE, refer to the Mentor Graphics Design Viewpoint Editor Users Manual and Reference Manual.

Figure 3.10 Pld_dve Dialog Box
Enter the design name in the Component Name field, or click on Navigator to browse a list of design names. If you invoked pld_dve from the Navigator window, the component is already selected.

If you click on the Navigator, you can select the component name, and the corresponding viewpoint name will appear in the Viewpoint Name field.
In the Select One field, select Simulation.

Select Custom if you want to open the selected viewpoint in DVE so that you can interact with it rather than accept the pld_dve default. Selecting custom invokes Mentor's DVE and opens the named viewpoint. You could use this to select a different model for a specific sub-module.
In the Viewpoint Name field, you can enter the viewpoint name if you do not want to use the default viewpoint.
In the PLD Technology field, select a technology.
Click on Invoke Stand-Alone DVE only if you want to invoke DVE to interact with Mentor's user interface instead.

This command brings up the DVE window to allow you to customize the viewpoint. For information on customizing a viewpoint, see the Mentor Graphics DVE user documentation.
Select OK to start pld_dve.

Pld_dve now generates a viewpoint with the same name as that entered in the Viewpoint Name field. It is in the format component_name/viewpoint_name.

You can also access pld_dve from a UNIX shell.

If you are converting a top-level XNF or EDIF netlist with pld_xnf2sim or pld_edif2sim, the simulation viewpoint is created for you automatically.

Simulating the Design

After creating the viewpoint, you can submit pure schematic designs to pld_quicksim for functional simulation.

To invoke pld_quicksim, double-click the left mouse button on the pld_quicksim icon in the Design Manager Tools window.

Alternatively, you can select the top-level component in the Navigator window and click the right mouse button to invoke pld_quicksim.

The PLD_QuickSim II dialog box, shown in the “PLD_QuickSim II Dialog Box” figure, appears on the screen. For more detailed information on the dialog box options, refer to the Mentor Graphics QuickSim documentation.

Figure 3.11 PLD_QuickSim II Dialog Box
In the Design field, enter the design name. If you selected the component in the Navigator window, the design name is already set.
In the Select Desired Mode box, click on No Cross-Probing, if it is not already selected (This is the default setting).

You can only select cross-probing for timing simulation for schematic designs, not for functional simulation. See the “Cross-Probing” section for more details about cross-probing.
In the Timing Mode field, select Unit for functional simulation.
In the Detail of “Unit” Timing Mode field, click on Hidden.
In the Simulator Resolution box, enter the smallest unit of time that you want to be visible in the simulator.

The smallest resolution allowed for Xilinx designs is 0.1 ns.
Click on OK.

Pld_quicksim now starts, and the QuickSim II window appears. The QuickSim II window functions as a waveform viewer; you can bring up the schematic and view the signals, or you can view the waveforms generated by the simulation. Consult the Mentor Graphics documentation for more information on how to view waveforms in this window.

Simulating Schematic Designs with LogiBLOX Elements

LogiBLOX creates a simulation model for LogiBLOX elements. However, you must still create a viewpoint on the top-level design with pld_dve before functionally simulating the design. Follow the instructions in “Creating the Viewpoint” section of the “Simulating Pure Schematic Designs” section in this chapter. Then submit the design to pld_quicksim, following the procedure given in the “Simulating the Design” section of the “Simulating Pure Schematic Designs” section in this chapter.

Simulating Schematic Designs with XNF Elements

To functionally simulate a pre-route XNF design, follow the steps in this section. The steps are illustrated in the following figure.

Figure 3.12 XNF Functional Simulation Flow

Creating the Design Component

Create the top-level design component as described in the “Creating the Design Component” section in this chapter. This provides an “anchor” for the converted design.

Converting the XNF File

The next step is to convert the XNF file to a simulation model.

In your schematic, create a symbol for each XNF element in your design.
Attach a FILE=xnf_file_pathname property to each symbol.
Double-click the left mouse button on the pld_xnf2sim icon in the Design Manager Tools window.

The resulting dialog box is shown in the following figure.

Figure 3.13 PLD XNF to Mentor Convert Dialog Box
Pld_xnf2sim uses all supporting XNF files from the directory in which the top-level XNF input file was submitted.
If the required XNF files are not in that directory, click Yes in the field asking “Select a group of XNF files from a list file?,” and specify the path name of a file that lists the path names of all needed XNF files. Each path name is specified on a separate line in this file, for example:

/x/y/z/abc.xnf /x/y/z/def.xnf
In the Synopsys XNF field, select No if the XNF does not come from Synopsys.
In the Top-level XNF Input File field, type the name of your top-level XNF file, or click on Navigator to find it.
In the Enter Name field, enter the name of the symbol that you created in step 1, or click on Navigator to find it.

NOTE
If the symbol has not yet been created, a Mentor component is created with an EDDM-single-object model. At this point, you can use Design Architect to create a symbol for it. Click on Open Symbol and specify the path name of this component. A symbol is automatically created. Check the symbol, add the file=xnf_file_pathname property, and save it if the XNF file represents the entire design (If it has EXT statements for IO pins.). However, if the XNF does not contain EXT statements, you must manually create the symbol and assign the pins. In this case, the simulation model (EDDM_single_object) created by pld_xnf2sim will not correspond with this symbol, and functional simulation must be done by converting the entire design to EDIF and submitting the EDIF to pld_edif2sim to create a top-level component and use pld_quicksim to simulate. This top-level component and all its submodules will be expressed in terms of SIMPRIM primitives rather than the Unified Library components used for design entry.
In the PLD Technology field, select the appropriate architecture.
Leave the Exit on Errors button enabled if you want the program to exit when it encounters an unresolved block. Otherwise, click on the Exit on Errors button and it changes to Continue (Ignore Errors).
In the Select Desired Simulation Model field, select EDDM.
In the “Enter additional directories to search” field, enter all the directory pathnames that the program should search to find EDIF, XNF, and NGO files that define blocks in your design that have the File property on them.
Click OK.

This procedure produces a single-object simulation model for the specified symbol component.

Creating the Viewpoint

If you are converting a top-level XNF or EDIF netlist with pld_xnf2sim or pld_edif2sim, the simulation viewpoint is created for you automatically.

Simulating the Design

The rest of the simulation procedure is the same as that described in the “Simulating the Design” section of the “Simulating Pure Schematic Designs” section earlier in this chapter.

Simulating Schematic Designs with EDIF Elements

To functionally simulate a pre-route EDIF design, follow the steps in this section. The steps are illustrated in the following figure.

Figure 3.14 EDIF Functional Simulation Flow

Creating the Design Component

Create the top-level design component as described in the “Creating the Design Component” section in this chapter. This provides an “anchor” for the converted design.

Converting the EDIF File

The next step is to convert the EDIF file to a simulation model.

In your schematic, create a symbol for each EDIF element in your design.
Attach a FILE=edif_file_pathname property to each symbol.
Double-click the left mouse button on the pld_edif2sim icon in the Design Manager Tools window.

The resulting dialog box is shown in the following figure.

Figure 3.15 PLD EDIF to Mentor Convert Dialog Box
Pld_edif2sim uses all supporting EDIF files from the directory in which the top-level EDIF input file was submitted.
In the EDIF source field, select Mentor, Synopsys, or Other to specify the source from which the EDIF was generated. Specify Other if the EDIF comes from a vendor other than Mentor or Synopsys. When selecting Other, you must ensure that the EDIF is compatible with Xilinx EDIF.
In the Top-level EDIF Input File field, type in the name of your top-level EDIF file, or click on Navigator to find it.
In the Enter Name field, enter the name of the symbol that you created in step 1, or click on Navigator to find it.

NOTE
If the symbol has not yet been created, a Mentor component is created with an EDDM-single-object model. At this point, you can use Design Architect to create a symbol for it. Click on Open Symbol and specify the path name of this component. A symbol is automatically created. Check the symbol, add the file=edif_file_pathname property, and save it.
In the PLD Technology field, select the appropriate architecture.
Leave the Exit on Errors button enabled if you want the program to exit when it encounters an unresolved block. Otherwise, click on the Exit on Errors button and it changes to Continue (Ignore Errors).
In the Select Desired Output field, select EDDM.
In the “Enter additional directories to search” field, enter all the directory pathnames that the program should search to find EDIF, XNF, and NGO files that define blocks in your design that have the File property on them.
Click OK.

This procedure produces a single-object simulation model for the specified symbol component.

If you are converting an EDIF with pld_edif2sim, the simulation viewpoint is created for you automatically.

Simulating the Design

The rest of the simulation procedure is the same as that described in the “Simulating the Design” section of the “Simulating Pure Schematic Designs” section earlier in this chapter.