Design Entry

Invoking Design Architect

You can use either the pld_da icon or the Navigator to invoke Design Architect from the Design Manager.

To invoke Design Architect with the pld_da icon in the Tools Window, double-click the left mouse button on the pld_da icon. A Design Architect window similar to that shown in the “Design Architect Window” figure appears but without displaying a schematic. You can use the Open Sheet icon in the Session Palette to open a schematic sheet.

If you want to load a specific design, you can invoke Design Architect from the Navigator as follows:

1. Select the design in the Navigator window and press the right mouse button.
   
   
2. Select Open pld_da from the Navigator pop-up menu.
   
   A Design Architect window similar to that shown in the following figure appears.
   
   

   Figure 3.1 Design Architect Window

Exiting Design Architect

To exit Design Architect, move the cursor to the title bar of the Design Architect window, press the right mouse button, and select Quit from the popup menu.

Loading a Schematic

If a design is not loaded into the schematic window, the Session Palette (session_palette) appears on the right-hand side of the Design Architect window. If one design is presently loaded and you want to also load another design, click on the Session icon in the schemataic_add_route Session Palette.

To load an existing schematic into the Design Architect window, follow these steps.

1. Click on the Open Sheet icon in the Session Palette.
   
   The Open Sheet dialog box appears, as shown in the following figure.
   
   

   Figure 3.2 Open Sheet Dialog Box

2. To find an existing design, type the path and name of the component or schematic in the Component Name field, or click on Navigator to find it.
   
   

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   NOTE

   If the component has not yet been created, open pld_da in the Tool Window. Then open a sheet from the Session Palette. In the Open Sheet dialog box, assign the component a name and click OK.

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3. In the Sheet field, type the name of the schematic sheet that you want to display.
   
   
4. In the Open As field, select Editable.
   
   
5. Click on OK.
   
   The schematic sheet now appears in the Design Architect window. The schematic number, name of the design, and sheet number appear in the title bar. The Session Palette changes to the Schematic Palette (schematic_add_route).
   
   

Creating the Design Component

When you save your schematic in Design Architect, the following items are created:

• A design.mgc_component.attr file
  
  
• A design component directory
  
  

The design component directory may contain schematic files, symbol files, and viewpoint files. The design directory and the design.mgc_component.attr file together are known as a Mentor component object.

Adding Components

Adding Xilinx library Components

1. To add a component from the Xilinx libraries, select XILINX Libraries from the Libraries pull-down menu.
   
   
2. In the Schematic Palette, click on the desired technology library.
   
   

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   NOTE

   You cannot mix old XC4000EX library components with XC4000X library components. Use Convert Design to convert XC4000EX designs to XC4000X before instantiating new XC4000X library components.

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3. Click on BY TYPE to select a category of element, or ALL PARTS to select a specific element.
   
   
4. Click on the desired element, move the cursor to the desired location on the schematic, and click on the left mouse button to place it.
   
   

Xilinx Libraries

In Design Architect, the Xilinx Libraries menu contains the Unified Libraries. The Unified Libraries are a collection of libraries that conform to standards set for the appearance, function, and naming conventions of the library elements. This standardization allows you to easily convert from one Xilinx architecture to another. You should use the primitives and the macros in the Unified Libraries to create new designs. Refer to the XACT Libraries Guide for detailed information on the Xilinx Libraries.

The Xilinx Libraries contain the following types of components:

• Primitives: These are pads and basic logic elements, such as gates, latches, flip-flops, buffers, and oscillators.
  
  
• Soft macros: These are schematics that contain primitives and other soft macros. Soft macros have pre-defined functionality and often have fixed mapping, placement, and routing to provide the most efficient use of resources and the fastest speed.
  
  

LogiBLOX allows you to synthesize common data functions such as addition, that are optimized for a particular family. Refer to the LogiBLOX User Guide for information on LogiBLOX components.

The following procedure describes selecting a component from the Unified Libraries and placing it in your schematic. Do not mix components from different technologies (families).

From within Design Architect, select and place library components as follows:

1. Select XILINX Libraries from the Libraries pull-down menu. The schematic palette is replaced by the Xilinx libraries menu palette.
   
   
2. Select the correct library for your design. A menu appears and you can select BY TYPE or ALL PARTS. If you select By Type, a list of the components organized into categories such as buffer, counter, or flip_flop appears. If you select All Parts, all the components are displayed in alphabetical order. Use the Page Up and Page Down keys to move up and down the list of components.
   
   
3. Select a component from the library list.
   
   
4. Move the cursor into the schematic window. An outline of the selected component appears.
   
   
5. Move the outline to the appropriate location and click the left mouse button to place the component.
   
   

Bus rippers are Mentor Graphics-supplied special components that connect nets to specific signals on a bus. You can obtain bus rippers by selecting the rip component in the Logic submenu in the Unified Libraries. These components are the same as rip components in the MGC Digital Libraries gen_lib.

A bus ripper consists of two pins. The narrow end is the wire end and the wide end is the bundle end. The wire end always connects to a net or smaller bus, and the bundle end connects to a bus. The bus ripper can tap all or a set of signals into a new bus. Refer to the following figure for an example of a bus ripper.

Figure 3.3 Bus Ripper

In Mentor, there are two types of bus rippers, implicit and explicit. An explicit ripper uses the RULE property to specify the index. The RULE property lets you specify a name for the net. An implicit ripper does not have a rule property and the name of the net must be the same as the name of the bus.

To add a bus ripper to a bus, perform the following procedure:

1. If you don't already have a bus in your system, add one and give it a name such as ADDR (31:0).
   
   
2. Draw a net to the bus.
   
   
3. In the Choose Bus Bit dialog box that opens, specify the bit number of the net that you want to rip.
   
   

   Figure 3.4 Choose Bus Bit Dialog Box

4. Design Architect automatically inserts a ripper which by default is implicit.
   
   
5. To specify a non-implicit ripper, open the Setup Ripper dialog box by doing one of the following:
   
   
   • Select the Setup Ripper menu
     
     
   • Select the Setup Ripper icon in the Schematic palette
     
     

     Figure 3.5 Setup Ripper Dialog Box

6. In the Setup Ripper dialog box, Select the Auto ripper mode and click OK.
   
   
7. Specify the bit in the Choose Bus Bit dialog box and the bus name if it is not already named.
   
   

An explicit ripper has a RULE property, which defines the bit or bits being tapped from the bus. By default, the RULE property is set to R, but you must change the property value to represent the bit or bits you want tapped from the bus.

To change the property value, perform the following procedure:

1. Select the wire end of the bus ripper part whose RULE property you want to change.
   
   
2. Access the Edit Window popup menu and select Properties Modify.
   
   
3. Select the RULE property and enter the desired property value in the Property Value box. For more information on bus rippers, refer to the “Schematic Design Tutorial” chapter in this Manual and the Design Architect User's Manual.
   
   

Adding Properties

Although a few differences exist when comparing PLD designs to other ASIC or board-level designs, PLD schematic design generally involves the same techniques used when you design other technologies. Most of these differences involve adding Xilinx PLD-specific attributes to schematic components. This information is used by the design implementation software during placement and routing of your design.

In Design Architect, adding Xilinx attributes is called property annotation. Property annotation is used to add design information called “properties” to schematics and symbols. These added properties describe characteristics of a component that are not identifiable from the schematic drawing alone. They provide information to the implementation tools during the processing of your schematic design.

Properties

This section describes the properties that are unique to Mentor or that are required when working with Xilinx PLDs using Mentor.

Properties, or attributes, are instructions placed on symbols or nets in an FPGA or CPLD schematic that allow you to control aspects of software processing. They express information specific to each design, unlike run-time options entered in the Xilinx Design Manager.

This section describes the properties that are unique to Mentor schematics or that are required. The Xilinx Libraries Guide describes the other attributes that you can place on a Mentor schematic.

Add the PINTYPE property to a pin to identify it as input or output for pld_dve. Pld_dve uses the PINTYPE property to determine the pin directionality of all of the symbol's pins. When adding PINTYPE properties, select PINTYPE from the list of properties and type in, out, or ixo for input, output, or bidirectional, respectively, in the value box.

Use the INST property to uniquely identify an instantiation of a component or symbol in a design. Design Architect assigns a default INST property to the symbol of each instantiation (I$1, I$2, and so forth), and the INST value is appended to the hierarchical path.

Use the COMP property to indicate that a simulation model exists for a primitive. All Xilinx primitives have a COMP property.

Do not place the COMP property on user symbols since COMP indicates that the symbol is a Xilinx library primitive.

Use the CYMODE property on the Carry Mode symbol to identify the mode for the dedicated carry logic in an XC4000 CLB.

Use the INTERNAL property to identify unbonded IOBs.

Adding Properties

Use the following procedure to add properties to instances, pins, or nets.

1. Select the instance, pin, or net.
   
   If you are applying a property to an instance, select the instance. Be sure nothing else is selected.
   
   If you are applying a property to a net, select the vertex where the output of a symbol connects to the net. Be sure you have selected only that vertex; a single star should appear at that location.
   
   
2. Press the right mouse button.
   
   The Instance popup menu should appear if you have selected an instance. The Net popup should appear if you have selected a net or a pin. If the Mixed Selection popup appears instead, you have more than one design object selected. Choose Unselect All, then select the instance or net and try pressing the right mouse button again.
   
   
3. Select the Properties Add Add Single Property command from the popup menu.
   
   The Add Property dialog box appears, as shown in the following figure.
   
   

   Figure 3.6 Add Property Dialog Box

4. In the Property Name box, type the name of the property, for example, OPT, or click on it in the Existing Property Name list.
   
   
5. Type the value, for example, OFF, in the Property Value box.
   
   

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   NOTE

   For some properties, the property name and the property value are identical.

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6. Because most properties take strings, select String in the Property Type field.
   
   
7. In the Visibility field, select On if you want the property to be visible.
   
   
8. In the field asking whether to attach the property to pins or vertices, select Vertices if you are attaching it to a net or an instance. Select Pins if you are attaching it to a pin.
   
   Body, pin, and net properties are always added to vertices.
   
   
9. Select OK.
   
   The ADD PR prompt bar appears.
   
   
10. Position the cursor where you want to place the property, usually above the component or net.
    
    
11. Click the left button to place the property.
    
    

Adding the Net Property to Nets

Use the Net property to label signals in your design. To add a Net property, you can either follow the instructions in the “Adding Properties” section or follow these steps:

1. Select all of the nets that you want to name.
   
   Unlike the procedure in the “Adding Properties” section, it is not necessary to select a single vertex for each net.
   
   
2. Press the right mouse button.
   
   The Net popup appears. If the Mixed Selection popup appears instead, select Other Menus, then select Net Menu.
   
   
3. Select Name Nets from the popup menu.
   
   The ADD PR bar appears.
   
   
4. Type the property value in the Property Value box.
   
   
5. Click OK.
   
   
6. Position the cursor where you want to place the property, usually above the component or net.
   
   
7. Click the left mouse button to place the property.
   
   
8. Repeat the netname entry for each net you have selected.
   
   

Modifying Property Values

You can only modify property values, not property names.

To modify a property's values, perform the following steps:

1. Select the entity whose property value you want to change.
   
   
2. Press the right mouse button to display the popup menu.
   
   
3. Select Properties Modify.
   
   A dialog box appears listing the properties of the selected object. The following figure shows an example.
   
   

   Figure 3.7 Modify Properties Dialog Box

4. Select the property that you want to modify.
   
   
5. Click on OK.
   
   The Modify Property dialog box is displayed, as shown in the following figure.
   
   

   Figure 3.8 Modify Property Dialog Box

6. Type the new value in the Value field.
   
   
7. Set any other options. Most of the time the default settings are appropriate.
   
   
8. Click on OK.
   
   

Entering Timing Specifications

The Mentor netlist writer program (ENWRITE) converts all property names to lowercase letters, and the Xilinx netlist reader EDIF2NGD then converts the property names to uppercase letters. To ensure references from one constraint to another are processed correctly, observe these guidelines:

• A TSidentifier name should contain only uppercase letters on a Mentor Schematic (TSMAIN, for example, but not TSmain or TSMain).
  
  
• If a TSidentifier name is referenced in a property value, it must be entered in uppercase letters. For example, the TSID1 in the second constraint below must be entered in uppercase letters to match the TSID1 name in the first constraint.
  
  TSID1 = FROM: gr1: TO: gr2: 50;
  TSMAIN = FROM: here: TO: there: TSID1: /2;
  
  

Creating New Groups from Existing Groups

The Mentor netlist writer program (ENWRITE) converts all property names to lowercase letters, and the Xilinx netlist reader EDIF2NGD then converts the property names to uppercase letters. To ensure references from one constraint to another are processed correctly, observe these guidelines:

• Group names should contain only uppercase letters on a Mentor Schematic (MY_FLOPS, for example, but not my_flops or My_flops).
  
  
• If a group name appears in a property value, it must also be expressed in uppercase letters. For example, the GROUP3 in the first constraint below must be entered in uppercase letters to match the GROUP3 in the second constraint.
  
  TIMEGRP GROUP1 = gr2: GROUP3;
  TIMEGRP GROUP3 = FFS: except: grp5;