Implementing Schematic Designs

Once you complete functional simulation for schematic designs, you are ready to implement your design. You perform implementation with the Xilinx Design Manager, pld_dsgnmgr, which you invoke from the Mentor Design Manager or from a UNIX shell. Pld_dsgnmgr first translates the design into a flattened or hierarchical netlist, then optimizes, places, and routes the design. It creates delay data for timing simulation and physical (bitstream) design data for downloading.

Design entry of pure schematic designs, or schematic designs with LogiBLOX elements, EDIF sub-modules, or XNF sub-modules produces an EDDM file that you must convert to EDIF with the pld_men2edif utility before implementing the design with pld_dsgnmgr. The following figure shows the design flow involved in implementing a design.

Figure 3.16 Design Implementation

Converting the EDDM Design

To convert your design to EDIF, follow these steps.

In the Mentor Design Manager, double-click the left mouse button on the pld_men2edif icon.

The dialog box shown in the following figure appears.

Figure 3.17 Mentor to EDIF Netlist Dialog Box
In the Component Name field, enter the component name, or click on Navigator to browse a list of design names.
In the From Viewpoint field, you can enter the viewpoint name if you do not want to use the default viewpoint. Alternatively, in step 2 you can select a viewpoint under the component.
Select the appropriate architecture for your design in the PLD Technology field.
Select the appropriate Bus Dimension Separator Style.

This is important if you are merging components from other design-entry tools into a single design. Choosing a bus-index delimiter lets you insure that the bus-index delimiters that pld_men2edif writes out are consistent with those of any other design-entry tools with which you are interfacing. Mentor EDIF uses parentheses. Synopsys EDIF uses angle brackets.
Click OK.

Pld_men2edif now produces an EDIF file that you can submit to the Xilinx Design Manager, pld_dsgnmgr. The output name is component_name.edif.

Implementing the Design

The Xilinx Design Manager is a graphical design-flow and project manager. The Xilinx Design Manager takes your design, represented by the EDIF file from pld_men2edif, and implements it in an FPGA or CPLD. You can also use the Xilinx Design Manager to generate timing information that you can import into QuickSim or ModelSim.

The Xilinx Design Manager, pld_dsgnmgr, can accept an EDIF file, or if your design is a pure XNF design, it can accept an XNF file.

For a more in-depth discussion of the flow, including advanced implementation options, see the Development System Reference Guide.

To implement your design follow these steps:

Within the Mentor Design Manager, select the EDIF icon for your design in the Navigator, then select Right Mouse Button Open pld_dsgnmgr. The Xilinx Design Manager appears as shown in the “Xilinx Design Manager” figure. The tool automatically creates a Xilinx project called your_design_name. Xilinx project information is kept in a file called xproj/your_design_name.prj by default.

Figure 3.18 Xilinx Design Manager
Each project is associated with objects known as “versions” and “revisions.” Versions represent logic changes in a design (for example, adding a new block of logic, replacing an AND gate with an OR gate, or adding a flip-flop); revisions represent different executions of the design flow on a single design version, usually with new implementation options (for example, higher place and route effort, a change in part type, or experimentation with new bitstream options).
Within the Xilinx Design Manager, select Design Implement.

The Implement dialog box opens as shown in the following figure and displays fields for part type, design version, and revision.

Figure 3.19 Implementation Dialog Box
The Xilinx Design Manager reads the part type from the design if it specified in the design.

If you wish to specify the part type manually, click the Select button to display a pull-down listing of available devices. Choose a family, a device, a package, and a speed grade. Click OK. The part number is inserted into the Part field in the Implement dialog box.
Click on Options. The Options dialog box appears as shown in the “Options Dialog Box” figure.

NOTE
The CPLD Options dialog box does not have a Configuration Template section, nor does it have a Produce Logic Level Timing Report checkbox.

Figure 3.20 Options Dialog Box
Click Browse next to the User Constraints field. Select the appropriate .ucf file from the design directory, then Click OK.
Under Optional Targets, make sure the following are selected:
- Produce Timing Simulation Data: This generates a back-annotated EDIF netlist that can be imported into the Mentor Graphics tools.
- Produce Configuration Data: This generates a programming bitstream suitable for downloading into the Xilinx device.
- Produce Post Layout Timing Report: This generates a timing report file based on how the design is actually routed.
  
  You can also select the following option (FPGAs only):
- Produce Logic Level Timing Report: This generates a preliminary (pre-place and route) timing report based on the number of logic levels in each signal path. Since it is generated before the place-and-route layout step, it does not contain information on device routing. Looking at this report before place and route can be useful for seeing how much “routing slack” you have in a design.
Select the Edit Template button on the right hand side of the Implementation field. The Implementation Options dialog box appears as shown in the following figure.

Figure 3.21 Changing EDIF Vendor Information
Select the Interface tab. In the Interface pane, look under Simulation Data Options and verify that Format is set to EDIF and that Correlate Simulation Data to Input Design is selected. In the Vendor field, select Mentor.
Click OK to return to the Options window.
Click OK to return to the Implementation dialog box.
In the Xilinx Design Manager window, verify that you have selected the current version and revision you wish to work on, then click Run. The Flow Engine comes up as shown in the following figure.

Figure 3.22 The Xilinx Flow Engine
The status bar shows the progress of the implementation flow with the following stages:
- Translate: Convert the design EDIF file into an NGD (Native Generic Design) file.
- Map: Group basic elements (bels) such as flip-flops and gates into logic blocks (comps). Also generate a logic-level timing report if desired.
- Place&Route: Place comps into the device, and route signals between them.
- Timing: Generate timing simulation data and an optional post-layout timing report.
- Configure: generate a bitstream suitable for downloading into and configuring a device
When the implementation completes, an Implementation Status box appears with:

Implementing revision ver1->rev1 completed successfully.

Click on View Logfile to display the logfile from Flow Engine. The report is displayed in vi. To exit the viewer, type :q! and press Return. Click OK in the Implementation Status dialog to return to the Xilinx Design Manager.

NOTE
To use another text editor, such as Emacs, as the report viewer, select File Preferences from the Xilinx Design Manager.

For schematic-based designs, the Xilinx Design Manager produces an EDN file, which is a post-route EDIF netlist file that expresses timing and simulation in SIMPRIM library elements instead of Unified Libraries elements. You can now submit the EDN file to pld_edif2tim to create a simulation model for timing simulation. This is described in the following section.