Timing Simulation for Schematic Designs

Timing simulation verifies design functionality by using delay information from the EDIF, VHDL, or Verilog file created during design implementation. It also describes how to perform a timing analysis with Mentor's QuickPath tool.

During design implementation, the Xilinx Design Manager can produce an EDIF (EDN) file. For EDIF files, the process of timing simulation consists of converting the EDIF netlist to a Mentor EDDM model, creating a component and a viewpoint, and simulating the design with pld_quicksim. The timing simulation process for EDIF files is shown in the “Timing Simulation for Schematics” figure.

The “Performing Timing Simulation” section of the “Schematic Design Tutorial” chapter illustrates the steps involved in timing simulation.

This section describes how to use QuickSim to perform timing simulation on designs described in EDIF.

Figure 3.23 Timing Simulation for Schematics

Creating the EDDM Model and the Viewpoint

The first step in performing a timing simulation on your design is to use the pld_edif2tim utility to convert the EDIF netlist created by the Xilinx Design Manager to a Mentor EDDM model. At the same time, pld_edif2tim automatically creates a viewpoint which is subsequently processed by pld_dve -s to prepare it for timing simulation.

1. Double-click the left mouse button on the pld_edif2tim icon in the Design Manager Tools window.
   
   The dialog box shown in the following figure appears.
   
   

   Figure 3.24 EDIF to Mentor Eddm Single Object Dialog Box

2. Enter the name of the EDN file in the EDIF Input File field, or click on Navigator to browse the available files.
   
   The component created from the EDN file is put into a design library called my_design_lib. If you have already implemented your design at least once, this directory already exists. If you don't wish to copy over it, move it to another directory before proceeding.
   
   
3. Click on OK.
   
   
4. Invoke DVE, by double-clicking the left mouse button on the pld_dve icon in the Design Manager Tools window.
   
   The dialog box shown in the following figure appears.
   
   

   Figure 3.25 Pld_dve Dialog Box

5. Enter the top-level component name created by pld_edif2tim in the my_design_lib directory.
   
   
6. Use the Navigate button to navigate all the way down to the “default” viewpoint and select the viewpoint.
   
   
7. Select the Simulation Button.
   
   
8. Select the appropriate technology from the PLD Technology box.
   
   
9. Click OK.
   
   

Simulating the Design

You can now submit the design to pld_quicksim for timing simulation.

1. To invoke pld_quicksim, double-click the left mouse button on the pld_quicksim icon in the Design Manger Tools window.
   
   The pld_quicksim dialog box shown in the following figure appears on the screen. For more detailed information on the dialog box options, refer to the Mentor Graphics documentation.
   
   

   Figure 3.26 PLD_QuickSim II Dialog Box

2. In the Design field, enter the name of the top-level design created by pld_edif2tim.
   
   
3. In the Select Desired Mode field, select Cross-Probing.
   
   Normally, you select cross-probing for back-end EDDM designs but not for front-end designs. You can only cross-probe back-end designs that contain either pure schematic or schematics that contain EDDM hierarchical models. You cannot cross-probe designs written in HDL or that contain HDL models. See the “Cross-Probing” section for more details about cross-probing.
   
   

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   WARNING

   In order for cross-probing to work, other sessions of Design Viewpoint Editor and QuickSim must be closed. Otherwise, the interprocess communication gets confused. This includes another user's session invoked by rlogin from another workstation.

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4. Set the timing modes as desired.
   
   
5. Click on OK.
   
   Pld_quicksim now simulates the design. The QuickSim graphical user interface appears. If you selected cross-probing, DVE is invoked as well.
   
   
6. In DVE, open the viewpoint of the front-end schematic design, that is, the viewpoint submitted to pld_men2edif.
   
   
7. Open the sheet of the design, and select signals that you wish to trace.
   
   These signals are automatically added to the QuickSim trace window. If you have a file that sets up your trace window and stimulus, use that instead. Any signals selected in the trace window select the same on the schematic on which they reside in the DVE window. If such sheets have not been opened in DVE yet, you must open them to see the selections.
   
   

Cross-Probing

Cross-probing is a way of cross-referencing between the original schematic and the timing simulation model after placement and routing. Once a Mentor design is translated, expanded, mapped, placed, and routed, you can extract the back-annotation information and create a hierarchical EDIF netlist. After you convert this EDIF to an EDDM model using pld_edif2tim, you submit it to pld_dve to create a viewpoint and then to pld_quicksim for timing simulation. The resulting data base preserves the design hierarchy, and although it is created in terms of the SIMPRIM library, most of the original net names are still available. You enable cross-probing by invoking QuickSim with the -cp option. This option invokes pld_dve as well as pld_quicksim. You then open the original design viewpoint in pld_dve and view the desired design sheet. If you display the original schematic in pld_dve, you can select nets on the original schematic and view them in the QuickSim trace window.

You may optionally create a schematic model using Mentor's schematic generator (sg) from the Eddm model created by pld_edif2tim. This schematic is only for viewing the backend schematic and is not required for the Xilinx flow to work. With cross-probing, you can use your original schematic for this purpose.

You should usually be able to reapply your original test vectors to the new Eddm_single_object design model for timing and/or functional simulation in QuickSim.

When you create the trace/list window in QuickSim, selecting signals from the original selected test vectors should cause the corresponding net on the original schematic sheet in pld_dve to be selected. If it is unselected in the trace/list window, it is also unselected on the original schematic.

If a net is selected in the pld_dve schematic sheet window, the net is automatically added to QuickSim trace window. If the net due to optimization or other complexities has been eliminated in the post-layout design, QuickSim issues an Error message of the type:

Error: $$add_traces returned error status at line 440 of file /tools/...

Error: Unable to resolve string '/ALU/I$10/C2' to a signal or expression

No trace is displayed for this net.

When a net is selected on the original schematic sheet in pld_dve and if the corresponding signal is already added to the trace/list window, the net will not be added again; instead, it is highlighted in the trace/list window.

Adding list windows in quicksim is your choice. List windows are not automatically created. If you do create a list window, it is your choice which signals to add to the list window. Opening a list window does not automatically show or add the signals from the trace window. However once you have added signals to the list window, selecting such signals will interact with the original schematic exactly the same way as the ones in trace window.

WARNING

In order for cross-probing to work, other sessions of Design Viewpoint Editor and QuickSim must be closed. Otherwise, the interprocess communication gets confused. This includes another user's session invoked by rlogin from another workstation to your workstation.

NOTE

If you flatten your design during netlist generation, you loose hierarchical aliases for signals that span multiple hierarchy levels; only the name of the signal at its highest level is preserved.

While 100% backannotation is possible, certain limitations of simulators, optimization process, and modelling of complex functions can make 100% back annotation impossible.

For more details on cross-probing, see the following sections:

• “Performing Timing Simulation” section of the “Schematic Design Tutorial” chapter
  
  
• “Invoking Pld_quicksim” section of the “Schematic Design Tutorial” chapter.
  
  

Performing a Timing Analysis

Use the Mentor Graphics QuickPath tool to perform static and slack timing analysis on schematic designs that have been prepared for timing simulation. This tool enables you to identify critical paths and evaluate modifications that can improve your circuit's performance. Use the timing analysis tool to determine possible changes to a circuit so that you can optimize its performance. Refer to the Mentor Graphics documentation for more information on QuickPath.

You can perform a timing analysis either before or after timing simulation; however, you may want to perform the timing simulation first to assure the design's functionality, then use QuickPath to determine the design's critical path.

NOTE

Running QuickPath on PLD designs is optional.

1. To start QuickPath, double-click the left mouse button on the QuickPath icon in the Design Manager Tools window.
   
   The dialog box shown in the following figure appears on the screen. For more information on the dialog box options, refer to the Mentor Graphics documentation.
   
   

   Figure 3.27 QuickPath Dialog Box

2. Enter the name of the design in the Design field, or click on Navigator to find the design.
   
   
3. Do not enter anything in the Symbol or Interface field unless the top-level design contains more than one interface. If the top-level design has more than one component interface table or symbol, you can specify the source by entering the name in the appropriate field.
   
   
4. In the QuickPath Setup field, select Manual unless you have saved a previous timing analysis environment and want to load that file that contains it.
   
   
5. In the Simulator Resolution box, enter the smallest unit of time that you want to be visible in the simulator.
   
   The smallest resolution allowed for Xilinx designs is 0.1 ns.
   
   
6. In the Set the MIN Scale, Set the MAX Scale, Set the SETUP Scale, and Set the HOLD Scale fields, click on No unless you want to perform a “corner” analysis.
   
   These fields set scaling values that govern the minimum propagation delay, the maximum propagation delay, the setup time, and the hold time, respectively. In a “corner” analysis, you use these scaling values to perform two timing analyses. The first analysis models a slow chip and the second models a fast chip. If a chip with values at both extremes of the timing spectrum successfully passes the timing analysis, it is likely that all chips with values in between will also pass. These scaling values allow you to look at the differences in timing due to the variations in device process, voltage, and temperature.
   
   
7. Click on OK to start the timing analysis.
   
   A session window with a menu bar, messages window, and Setup/Analysis palette now opens.
   
   Click on Open Sheet to display the top-level design, and then proceed with the timing analysis.