Performing Timing Simulation

Timing simulation uses the block and routing delay information from the routed design to give a more accurate assessment of the behavior of the circuit under worst-case conditions. Also, since the delay-annotated timing netlist is different from the original schematic design, the timing simulation uses a process called cross-probing to allow you to view simulation results on your schematic. In this section, you perform a timing simulation of the Calc design by first preparing the design using pld_edif2tim. Once this has been done, you run pld_quicksim with cross-probing to trace waveforms and annotate results onto your original schematic.

Using Pld_edif2tim to Prepare a Timing Simulation

Pld_edif2tim reads a routed EDN file and back-annotates the delays to the schematic. This includes a number of steps, all of which are automatically run by the pld_edif2tim script. This script is represented by the pld_edif2tim icon in pld_dmgr. The files necessary for back-annotation have either been created in the Design Architect tutorial or are included in the solution directories.

Use pld_edif2tim to prepare the design for timing simulation as follows:

1. In pld_dmgr, use the Navigator to find and select the EDN time_sim icon.
   
   This represents the timing-annotated netlist generated by the Xilinx Design Manager.
   
   

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   NOTE

   There may be two similar looking types of icons, one marked EDIF and the other marked EDN. An EDIF file represents a netlist translated from the original schematic, while an EDN file represents a netlist translated from a routed NCD file. Be sure you select an EDN file to prepare for timing simulation.

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2. Select Right Mouse Button Open pld_edif2tim.
   
   A dialog box appears. Design Manager automatically fills in the dialog box with the name of the EDN file.
   
   
3. Verify that the Replace existing routed design library field is set to NO.
   
   On subsequent executions of pld_edif2tim, you may set this to YES if you are overwriting a previous timing model.
   
   
4. Press return or select OK to execute the command.
   
   The script produces a shell and runs in it.
   
   

Examining the Pld_edif2tim.log File

Examine the pld_edif2tim.log file as follows:

1. In pld_dmgr, select Right Mouse Button Update Window.
   
   The window is updated with the files that pld_edif2tim generated.
   
   
2. Find the pld_edif2tim LOG file and select it with the left mouse button.
   
   
3. Choose Right Mouse Button Open Editor to open the file in the editor.
   
   No errors or warnings should be reported. For a short summary of the commands executed by pld_edif2tim during the timing flow, see the “Command Summaries” section at the end of this chapter. The timing flow is always the same since the starting point is always a routed EDN file with delays.
   
   
4. When you have finished looking at the file, close the Editor window.
   
   

Using Pld_dve

As with functional simulation, the timing-annotated netlist must also have a viewpoint associated with it.

1. In your design directory, you should now see a directory called calc_lib. Double-click on this directory icon to descend into it.
   
   
2. Select the calc component (which should be at the very bottom on the icon listing) with the left mouse button.
   
   
3. Invoke pld_dve on the simulation netlist component by selecting Right Mouse Button Open pld_dve.
   
   A dialog box appears. Note that the component name, Calc, is entered automatically with a fully qualified path.
   
   

   Figure 9.77 Invoking Pld_dve for Timing Simulation

4. Select the appropriate PLD Technology from the listing, e.g., XC4000E, as shown in the figure above. (Leave other options set to their defaults, as shown in the figure.)
   
   
5. Click OK to execute the pld_dve script.
   
   
6. Once pld_dve completes, dismiss the shell window in which it has executed.
   
   

Invoking QuickSim for Timing Simulation

1. With the timing-annotated calc component in the calc_lib directory still selected, invoke pld_quicksim by selecting Right Mouse Button Open pld_quicksim.
   
   A dialog box appears. The component name, Calc, is entered automatically with a fully qualified path.
   
   

   Figure 9.78 Invoking Pld_quicksim for Timing Simulation

2. Select desired mode as Cross-Probing.
   
   This allows QuickSim to use the back-annotated timing model in QuickSim, while allowing you to view the original schematic in DVE. This process is necessary because your original schematic is expressed in Unified libraries, while the back-annotated timing model is generated using simulation primitives.
   
   
3. Select the Constraint option for Timing mode.
   
   
4. Select the Visible option for Detail of `Constraint' timing mode.
   
   A new set of buttons appears in the dialog box.
   
   
5. Select Typ for Timing mode.
   
   This specifies the use of the back-annotated timing information.
   
   
6. Select Messages for Constraint mode.
   
   
7. Leave the rest of the buttons set at their defaults, and press return to start QuickSim.
   
   For more information on these other options, refer to the Mentor Graphics documentation on QuickSim. For most Xilinx simulations, the above setup is appropriate.
   
   The Design Viewpoint Editor (DVE) appears and gives an informational message reading,
   
   To start the cross-probing process, ...
   
   
8. Click Close in this message window.
   
   
9. Resize the DVE window so that it is almost as large as the entire screen.
   
   The QuickSim window also appears.
   
   
10. Resize the QuickSim window so that it is almost as large as the entire screen, allowing space for you to click on the DVE window to make it active and display in the foreground.
    
    
11. Bring the DVE window to the foreground and select OPEN DESIGN VIEWPOINT from the palette.
    
    
12. In the dialog box, enter the name of the original component in the Component field, e.g., $XILINX_TUTORIAL/calc_sch/calc. (Do not enter the name of the simulation model, $XILINX_TUTORIAL/calc_sch/calc_lib/calc.)
    
    
13. Click OK to load the original viewpoint.
    
    
14. Select OPEN SHEET from the palette to open the top-level Calc schematic.
    
    
15. To see the cross-probing process in action, click on the CLK net attached to the CLOCKGEN component.
    
    A few seconds after this net is selected in DVE, a Trace window appears in QuickSim listing the CLK net.
    
    
16. Bring the QuickSim window to the foreground to see the Trace window.
    
    
17. Select Transcript Replay from the QuickSim menu bar.
    
    
18. From the dialog box, choose the calc_4ke.do file. (Depending on your target device, select calc_3ka.do, calc_5k.do, or calc_9k.do.)
    
    This replays a transcript file similar to the one created earlier. This transcript file opens the design; opens Trace and Monitor windows with the correct signals; assigns stimulus to the signals; and then runs the simulation. It should be obvious when you look at the Trace output that real delay values are being used. It may be useful to view the transcript file using the editor in pld_dmgr or another editor.
    
    The figure below shows how DVE and QuickSim may look like running side by side.
    
    

    Figure 9.79 Cross-Probing with DVE and QuickSim

19. After examining the waveforms in timing simulation, close both the QuickSim and DVE windows.