Using the Xilinx Design Manager

The Xilinx Design Manager is a graphical design-flow and project manager. The Xilinx Design Manager takes your design, represented by the EDIF file from pld_men2edif, and implements it in an FPGA or CPLD. You can also use the Xilinx Design Manager to generate timing information that you can import into QuickSim or ModelSim.

This section gives a brief overview of the design implementation flow. For a more in-depth discussion of the flow, including advanced implementation options, see the Development System Reference Guide.

1. Within the Mentor Design Manager, select the Calc EDIF icon in the Navigator, then select Right Mouse Button Open pld_dsgnmgr.
   
   The Xilinx Design Manager appears as shown. The tool automatically creates a Xilinx project called calc. Xilinx project information is kept in a file called xproject/calc.prj by default.
   
   

   Figure 9.72 Xilinx Design Manager

   Each project has associated with it objects known as “versions” and “revisions.” Versions represent logic changes in a design (for example, adding a new block of logic, replacing an AND gate with an OR gate, or adding a flip-flop); revisions represent different executions of the design flow on a single design version, usually with new implementation options (for example, higher place and route effort, a change in part type, or experimentation with new bitstream options). In the next stage, you make a new version and revision on which you run the implementation design flow.
   
   
2. Within the Xilinx Design Manager, select Design Implement, which gives you the Implement dialog box, with fields for part type, design version, and revision as shown in the following figure.
   
   

   Figure 9.73 Implementation Dialog Box

   In the current release of software, the Xilinx Design Manager does not read the part type from the design.
   
   

   ---

   NOTE

   The PART property in the CONFIG symbol does get read properly when processed from the system prompt, if the “-p” command-line option is omitted from NGDBUILD and MAP. (See the “Command Summaries” section of this chapter.)

   ---

3. Click the Select button to display a pull-down listing of available devices.
   
   
4. Choose a Family of XC4000E, a Device of XC4003E, a Package of PC84, and a Speed Grade of -4.
   
   
5. Click OK.
   
   The part number is inserted into the Part field in the Implement dialog box.
   
   
6. Click on Options.
   
   The Options dialog box appears.
   
   

   ---

   NOTE

   The CPLD Options dialog box does not have a Configuration Template section, nor does it have a Produce Logic Level Timing Report checkbox.

   ---

   Figure 9.74 Options Dialog Box

7. Click Browse by the User Constraints field.
   
   
8. Select the calc_4ke.ucf file from the design directory, then Click OK.
   
   
9. Under Optional Targets, make sure the following are selected:
   
   
   • Produce Timing Simulation Data - This generates a back-annotated EDIF netlist that can be imported into the Mentor Graphics tools.
     
     
   • Produce Configuration Data - This generates a programming bitstream suitable for downloading into the Xilinx device.
     
     
   • Produce Post Layout Timing Report - This generates a timing report file based on how the design is actually routed.
     
     You can also select the following option (FPGAs only):
     
     
   • Produce Logic Level Timing Report - This generates a preliminary (post-map, pre-place and route) timing report based on the number of logic levels in each signal path. Since it is generated after the mapping step but before the place-and-route layout step, it does not contain information on device routing. Looking at this report before place and route can be useful for seeing how much “routing slack” you have in a design.
     
     
10. Under Program Option Templates Implementation, select Edit Template.
    
    The XC4000 Implementation Options dialog box appears as shown.
    
    

    Figure 9.75 Changing EDIF Vendor Information

11. Select the Interface tab.
    
    
12. In the Interface pane, look under Simulation Data Options and verify that Format is set to EDIF and that Correlate Simulation Data to Input Design is selected.
    
    
13. In the Vendor field, select Mentor.
    
    
14. Click OK to return to the Options window.
    
    
15. Click OK to return to the Implementation dialog box.
    
    
16. Verify that the version is “ver1” and the revision is “rev1” then click Run.
    
    The Flow Engine comes up as shown in the figure.
    
    

    Figure 9.76 The Xilinx Flow Engine

    The status bar shows the progress of the implementation flow with the following stages:
    
    
    • Translate - convert the design EDIF file into an NGD (Native Generic Design) file
      
      
    • Map - group basic elements (“bels”) such as flip-flops and gates into logic blocks (“comps”); also generate a logic-level timing report if desired
      
      
    • Place&Route - place comps into the device, and route signals between them
      
      
    • Timing - generate timing simulation data and an optional post-layout timing report
      
      
    • Configure - generate a bitstream suitable for downloading into and configuring a device
      
      When the implementation completes, an Implementation Status box displays:
      
      Implementing revision ver1->rev1 completed successfully.
      
      
17. Click on View Logfile to display the logfile from the Flow Engine.
    
    The report is displayed in vi.
    
    
18. To exit the viewer, type :q! and press Return.
    
    
19. Click OK in the Implementation Status dialog to return to the Xilinx Design Manager.
    
    

    ---

    NOTE

    To use another text editor, such as Emacs, as the report viewer, select File Preferences from the Xilinx Design Manager.

    ---