Using Pld_men2edif

Once your design is verified to be functionally correct, you use pld_men2edif, a tool in the Mentor Graphics Design Manager, to translate your Mentor design into a Xilinx-ready EDIF netlist. Running pld_men2edif is always the first step in implementing a design. Whenever you make changes to your schematic, you must run pld_men2edif again so that the Xilinx software can process those changes.

When you run pld_men2edif from the Mentor Design Manager, the following dialog box appears:

Figure 9.70 Pld_men2edif Dialog Box

Here is an explanation of some of the fields and buttons in the pld_men2edif dialog box.

Component Name - Enter the name of the component that you want to process here.
From Viewpoint - If you are an advanced Mentor Graphics designer who uses viewpoints to organize design models and properties, enter the viewpoint name that you wish to use for this EDIF translation. If you do not use or are not familiar with viewpoints, leave this field blank and pld_men2edif will use a default value.
Forward Referencing of EDIF component libraries - This option applies only in rare situations where design hierarchy has been structured in such a way that circular or recursive references exist. Normally, this option is set to Off.
Output EDIF Bus Dimension Separator Style - This determines how bus-index delimiters are written into the output EDIF file. This is important if you are merging components from other design-entry tools into a single design. Choosing a bus-index delimiter lets you insure that the bus-index delimiters that pld_men2edif writes out are consistent with those of any other design-entry tools with which you are interfacing.

Since this design has been fully captured in Mentor Graphics, you need not worry about what type of bus delimiters are used. You may leave this setting on the default (PARENTH).
PLD Technology - Select the architectural family from this list.
HELP - If the HELP button is clicked, a short help listing is produced by the pld_men2edif script.

Perform the following steps to create an EDIF netlist for Calc:

Double-click on the pld_men2edif icon in Design Manager.
For the Component Name, type $XILINX_TUTORIAL/calc_sch/calc as shown above.
Select the architecture in the PLD Technology field, e.g., XC4000E.
Select OK.

This opens a new shell window where pld_men2edif runs and reports its progress. When pld_men2edif has completed, the following should appear at the bottom of the shell window:

pld_men2edif ended with return code 0 Done.
Dismiss the pld_men2edif shell window by typing Ctrl-C in it or by selecting Close from the window's control menu (accessed through the button on the left side of the title bar).

NOTE
The output of pld_men2edif may be sent to the window from which the pld_dmgr was originally invoked. This behavior is dictated by the $MGC_TERMINAL_WINDOW environment variable; see the Mentor Graphics documentation for more details.

Examining Pld_men2edif Output Files

In addition to the EDIF netlist, pld_men2edif also creates a pld_men2edif.log file. This file contains a transcript of the processing done by pld_men2edif. If the program fails to generate an EDIF netlist, any errors encountered are logged in this file.

Examine the pld_men2edif.log file for the Calc design as follows:

Select the Navigator window.
Choose Right Mouse Button Update Window.

This updates the Navigator window to display the new files created by pld_men2edif, including an EDIF file for Calc, and a log file for pld_men2edif.

Figure 9.71 Files Created by Pld_men2edif
Select the LOG icon labeled pld_men2edif and choose Right Mouse Button Open Editor.

A window appears displaying the log file.
When you are done viewing the log, close the window.

NOTE
You can change the display font in this window by selecting View Fonts.