This section applies only to FPGA designs. If you are targeting a CPLD such as an XC9000 device, skip to the “Making Incremental Design Changes” section.
At this point in the tutorial, the design process is complete. If you would like to see how the design has been implemented by the Xilinx software, you can take a graphic look at your placed and routed design using the Editor for Programmable Integrated Circuits, or EPIC. You can access EPIC from the Xilinx Design Manager.
EPIC provides several useful functions, such as:
Figure 9.80 EPIC Icon |  |
EPIC is explained in a separate tutorial. See the “EPIC Tutorial” section of the EPIC Reference/User Guide. Before starting this tutorial, be sure to select the ver1 
rev1 revision of the design in the project view
