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Performing Functional Simulation

Functional simulation is performed before design implementation to verify that the schematic that you have designed is logically correct. All components in the Calc design have built-in simulation models so little pre-processing is necessary. However, every top-level schematic design in Mentor Graphics must have a simulation viewpoint before you can simulate it in QuickHDL Pro. The viewpoint describes how a design should be interpreted, including what components in the design are primitives, as well as how components within the design hierarchy should be modeled.

NOTE

The following instructions refer to two related but different programs: ModelSim and QuickHDL Pro. ModelSim is Mentor Graphics' HDL-only simulator, while QuickHDL Pro is a co-simulation tool that runs both ModelSim to simulate the HDL portions of a design and QuickSim to simulate the schematic portions. QuickHDL Pro runs a process known as a FlexSim backplane through which the two “solvers” (ModelSim and QuickSim) communicate with each other.

Also note that the instructions that follow do not have detailed information on basic QuickSim operations such as selecting nets and displaying Trace and List windows. For information on these procedures, please refer to the “Schematic Design Tutorial” chapter.

Using Pld_dve

To use the PLD Design Viewpoint Editor to generate a design viewpoint to tell QuickSim (as run by QuickHDL Pro) how to interpret certain Xilinx-specific design properties, follow these steps.

  1. Select the calc design object from the appropriate directory in the Navigator window.

  2. Invoke pld_dve on the design by selecting Right Mouse Button Open pld_dve.

    A dialog box appears. Note that the component name, Calc, is entered automatically with a fully qualified path.

    Figure 10.9 Invoking Pld_dve for Functional Simulation

  3. Select the XC4000E PLD Technology from the listing as shown in the figure above. (Leave other options set to their defaults, as shown in the figure.)

  4. Click OK.

    The pld_dve script executes.

  5. Once pld_dve completes, dismiss the shell window in which it executed.

Invoking QuickHDL Pro

To invoke QuickHDL Pro for functional simulation on the Calc design, follow these steps:

  1. Select the Calc design object in the Navigator window.

  2. Invoke QuickHDL Pro on the design by selecting Right Mouse Button Open QHDL_Pro.

    A dialog box appears. Note that the component name, Calc, is entered automatically with a fully qualified path.

  3. Since the top-level Calc design is a schematic (EDDM model), verify that EDDM Design is the design set to Invoke on.

    Figure 10.10 Invoking QuickHDL Pro for Functional Simulation

    Note the OPTIONS category buttons. These buttons allow you to set options for QuickHDL Pro, as well as for each of the two simulation “solvers” (ModelSim and QuickSim). Each button brings up its own set of options in the OPTIONS panel. Each set of options is independent of the other two sets of options, and options in all three panels are applied concurrently when QuickHDL Pro is run.

  4. In the QuickHDL Pro dialog box, select OPTIONS category ModelSim to see the ModelSim options.

    Figure 10.11 ModelSim Options

  5. Under ModelSim Initialization file, enter:

    $XILINX_TUTORIAL/calc_sot/modelsim.ini

  6. Under ModelSim Logical Library, enter:

    work

    NOTE

    The ModelSim initialization file defaults to the modelsim.ini file in the working directory. The ModelSim logical library defaults to the “work” directory as called out in the initialization file.

  7. In the QuickHDL Pro dialog box, select OPTIONS category QuickSim to see the QuickSim options.

    The Unit timing mode should already be set, since this is the default. This tells the QuickSim solver to run in functional-simulation mode.

    Figure 10.12 QuickSim Options

  8. In the QuickHDL Pro dialog box, select OPTIONS category ModelSim and note that the settings you put in the ModelSim Options panel are still in place.

  9. Click OK to invoke the QuickHDL Pro simulator.

    Two windows open, QHPro(QuickSim) and QHPro(QuickHDL). These represent the QuickSim and ModelSim simulation solvers, respectively, running within the integrated QuickHDL Pro environment.

Viewing the Calc Schematic

When QHPro(QuickSim) starts, no schematic windows are open. Open a window and view the top-level schematic for the Calc design. Displaying the schematic is convenient for viewing back-annotation during the simulation.

Figure 10.13 Top-Level Calc Schematic

  1. To open a window containing the Calc schematic, select OPEN SHEET from the palette.

    This automatically opens the top-level sheet for Calc.

  2. Select the ALU symbol, then select Right Mouse Button Open Down.

    If this were a schematic module, the ALU schematic would appear in the QuickSim window. Instead, a Source window appears displaying the ALU VHDL description. This window is actually displayed through the ModelSim solver.

    Figure 10.14 ALU Source Window

Viewing and Navigating the VHDL Hierarchy

ModelSim allows you to view the design hierarchy of the HDL portion of a mixed design. To see this hierarchy and its associated signals follow these steps:

  1. From the QHPro(QuickHDL) menu bar, select View Structure.

    The Structure window appears as shown. Since the ALU source code is displayed in the Source window, the ALU entity is highlighted.

  2. Select View Signals to display the Signals window which shows a list of all signals underneath the ALU entity.

    Figure 10.15 Structure and Signals Windows

  3. With the left mouse button, select the seg7dec(behavior) entity in the Structure window.

    Notice that the Source window now changes to display the SEG7DEC VHDL file, and the Signals window changes to display the associated signals.

  4. Select the top-level calc_qsim(structure) entity in the Structure window.

    Notice that the Source window displays VHDL code even though the top level was originally drawn on a schematic. This VHDL file was written by QuickHDL Pro upon invocation so that ModelSim could simulate all instantiated VHDL modules from the top level.

  5. Reselect the alu (behavior) module in the Structure window.

    The Signals listing displays the ALU signals. Note that buses in the Signals listing have “+” icons next to them. If you click on one of these icons, it changes to a “-” icon, and the list expands to include all bit signals within the corresponding bus.

  6. Click the “-” icon to collapse the listing.

  7. Select the following signals in the Signals window. You may have to scroll down the list to see them all.

    clk
    ce
    opcode
    q
    stack
    stackop
    swdata

    You can select a collection of signals by clicking on the first signal name with the left mouse button, then clicking on subsequent signal names with the middle mouse button. If you select a signal name you don't want selected, click on the signal name again with the middle mouse button to unhighlight it.

    The waveforms for these signals can be traced in a ModelSim Wave window.

  8. In the Signals window, select Wave Selected signals.

    The Wave window appears as shown. Since the simulation has not yet been run, no waveforms are displayed.

    Figure 10.16 Wave Window at Time 0

In the next section, you complete the functional simulation and view the waveforms in the Trace (QuickSim) and Wave (ModelSim) windows.

Completing the Functional Simulation

You can automate the simulation by using a QuickSim command file. A “dofile,” calc_4ke.do, has been supplied with this tutorial for this purpose. This file opens Trace and List windows, sets up simulation vectors, and runs the simulation for a time duration of 3,400 ns. Use it as follows:

  1. From the QuickSim menu bar, select MGC Transcript Replay.

  2. In the dialog box, enter calc_4ke.do and click OK.

    The functional simulation runs automatically with Trace and List windows set up in the QuickSim window. Note that the Wave window under ModelSim is also updated to reflect the signals underneath the ALU component.

    NOTE

    For more specific information on using QuickSim features, see the “Schematic Design Tutorial” chapter. The simulation command file executed here is similar to the one run in that chapter.

  3. If the signal names and values in the Wave window are not fully visible, drag the divider between the signal list and the waveforms to see more of the signal names.

  4. You can use the scroll bars to view different parts of the simulation in the Wave window. You can also zoom in and zoom out by selecting from the Zoom menu.

  5. As with the Signals windows, the signal listing in the Wave window is expandable and collapsible. Click the “+” icon beside the /\/ARITH\/swdata signal name to view the individual signal waveforms in the Wave window.

    Figure 10.17 QuickSim Trace and ModelSim Wave Windows

  6. The SWDATA waveform corresponds to the lower four bits of the SWITCH(6:0) bus on the top-level schematic. SWITCH(3:0) is connected to the SWDATA(3:0) port on the ALU in the top-level schematic.

    Verify that the SWDATA value in the Wave window corresponds to the lower four bits of SWITCH(6:0) in the QuickSim Trace window.

    NOTE

    You can make this task a easier by selecting the SWDATA signal in the Wave window, then choosing Prop Signal from the menu bar. Select Radix: Hex, then Apply. The hexadecimal value displayed in the Wave window now matches up with the lower-order hexadecimal digit from the SWITCH(6:0) value.

  7. Close the QuickSim and ModelSim applications by choosing one of the two application windows and selecting Quit or Exit (depending on your workstation platform) from its control menu (the drop-down menu on the titlebar). It is not necessary to save any simulation results.

    NOTE

    Since both QuickSim and ModelSim are bound to the same process, closing one application automatically closes the other.

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