Completing the Calc Design

To complete the tutorial design, you need to link VHDL entities to symbols in the schematic using Vcom and Design Architect.

If you need to stop the tutorial at any time, be sure to save your work as follows:

Select Check Sheet from the menu bar.

A window appears containing the results of the design rule check.
After reviewing the contents of this window, close it and reselect the schematic window.

WARNING
It is important to check your design first before saving it.
Select File Save from the menu bar to save the design.

Design Description

The Calc design is a four-bit processor with a stack. The processor performs functions between an internal register and either the top of the stack or data input from external switches. The results of the various operations are stored in the register and displayed in hexadecimal on a seven-segment display. The top value in the stack is displayed in binary on a bar LED. A count of the items in the stack is displayed as a “gauge” on another bar LED.

In this tutorial, you create a new symbol for the SEG7DEC component from its associated seg7dec.vhd description, then instantiate that symbol onto the Calc schematic. You then link an existing ALU symbol to its associated alu.vhd description. A CONFIG block and a STARTUP block have already been added to the Calc design as well. For more information on using CONFIG and STARTUP, see the “Schematic Design Tutorial” chapter.

The design consists of the following functional blocks:

ALU - The arithmetic functions of the processor are performed in this block. This block is defined by the VHDL file alu.vhd.
CONTROL - The opcodes are decoded into control lines for the stack and ALU in this module.
STACK - The stack is a four-nibble storage device. It is implemented using synchronous RAM in the XC4000E design.
DEBOUNCE - This circuit debounces the “execute” switch, providing a one-shot output.
SEG7DEC - This block decodes the output of the ALU for display on the 7-segment decoder. You generate the symbol for this module from its behavioral VHDL description in seg7dec.vhd.
CLOCKGEN - This block uses an internal oscillator circuit in XC4000E devices to generate the clock signal.
BARDEC - This block shows how many items are on the stack on a “gauge” of four LEDs.
SWITCH7 - This is a user-defined module consisting of seven input flip-flops used to latch the switch data.

NOTE

Basic Xilinx design concepts such as assignment of pin properties, use of STARTUP and CONFIG, and incremental design methodology as well as details about Xilinx device architecture are not covered in this chapter. For more information on these topics, see the “Schematic Design Tutorial” chapter.

Adding the SEG7DEC Component

On the Calc schematic, notice a space near the upper-right corner of the schematic between the ALUVAL(3:0) bus and the inputs to seven OBUF elements that feed LED outputs A through G. This is where the SEG7DEC symbol must be placed.

This component has a VHDL file, seg7dec.vhd, that describes its behavior. In this exercise, you compile the seg7dec.vhd file for simulation, generate a symbol for it, then instantiate the entity into the Calc schematic so that it may be simulated and built into the implemented device.

Compiling the VHDL Entity

To compile the VHDL file for SEG7DEC, follow these steps:

Take a look at the src/seg7dec.vhd file with the text editor you normally use.

This entity includes a case statement that decodes a four-bit number into a set of seven signals suitable for display on a seven-segment LED display. The src/seg7dec.vhd file is as follows:

process (Q) 
     begin 
       case Q is 
         when "0000" => DISPLAY <= "0000001"; 
         when "0001" => DISPLAY <= "1001111"; 
         when "0010" => DISPLAY <= "0010010"; 
         when "0011" => DISPLAY <= "0000110"; 
         when "0100" => DISPLAY <= "1001100"; 
         when "0101" => DISPLAY <= "0100100"; 
         when "0110" => DISPLAY <= "0100000"; 
         when "0111" => DISPLAY <= "0001101"; 
         when "1000" => DISPLAY <= "0000000"; 
         when "1001" => DISPLAY <= "0000100"; 
         when "1010" => DISPLAY <= "0001000"; 
         when "1011" => DISPLAY <= "1100000"; 
         when "1100" => DISPLAY <= "0110001"; 
         when "1101" => DISPLAY <= "1000010"; 
         when "1110" => DISPLAY <= "0110000"; 
         when others => DISPLAY <= "0111000"; 
       end case; 
   end process;

Close the src/seg7dec.vhd file.
To create a VHDL work library where compiled entities will reside, type the following at the system prompt from within the $XILINX_TUTORIAL/calc_sot directory:

vlib mywork

A library directory called “work” now exists in the tutorial project directory.
Map this directory to “work” so that the VHDL compilation programs can recognize it:

vmap work mywork

You should now have a new file in your tutorial directory called modelsim.ini, which contains the following library entry:

[Library] work = work

This allows the VHDL-simulation programs to recognize this as the working directory.
Compile the src/seg7dec.vhd file with the vcom command:

vcom -qhpro_syminfo src/seg7dec.vhd

The -qhpro_syminfo option tells VCOM to write out information needed by the Design Architect Symbol Generator.
With the Calc schematic still open in Design Architect, select Miscellaneous Generate Symbol from the menu bar.
In the Generate Symbol dialog box that appears, select Choose Source Entity.

The dialog box fields change as shown in the Generate Symbol dialog box.

Figure 10.3 Generate Symbol Dialog Box

In the Generate Symbol dialog box, make sure the fields are set as shown in the following table:

Table 10_2 Generate Symbol Settings for SEG7DEC

Field	Value
QVHDL InitFIle	$XILINX_TUTORIAL/calc_sot/modelsim.ini
Lib. Logical Name	work
Entity Name	seg7dec
Deflt. Architecture	[”behavior”, “QVHDL arch”, [“qvhpro”]]
Place Comp. in Dir.	$XILINX_TUTORIAL/calc_sot
Pin Spacing	2
Shape Arguments	[2,2]
Sort Pins?	Yes
Replace existing?	No
Activate symbol?	No

NOTE

You can select the architecture setting from a list by click on the Choose Arch button. Since only one architecture has been compiled for the SEG7DEC entity, you may also leave this field blank.

Click OK.

After a few moments, the Symbol Editor appears with the newly created SEG7DEC component. Note the properties attached to this symbol and its pins. These properties allow the underlying entity and the upper-level schematic portion to be simulated concurrently in QuickHDL Pro.

NOTE
If you get the error “Entity source work_library/_parsed.vhd does not exist,” make sure you specified the -qhpro_syminfo option on the VCOM command line.
Add “SEG7DEC” text to the symbol as shown. (If you do not know the procedure for this, refer to the instructions in the “Schematic Design Tutorial” chapter.)

Figure 10.4 Generated SEG7DEC Symbol
All symbols that have an associated non-schematic model must have a FILE property attached to them so that the Xilinx netlister (NGDBUILD) can incorporate these portions of the design into the implemented design. The value of this property is the actual filename of the submodule netlist. This filename can have one of several different extensions, based on the netlist format it uses.

Table 10_3 Common FILE Property Extensions

Extension
Netlist Format

.edif
Generic Xilinx-compatible EDIF 2.0

.xnf
Generic XNF (Xilinx Netlist Format) 6.x

.sedif
Synopsys Xilinx-compatible EDIF 2.0

.sxnf
Synopsys XNF 6.x

The presynthesized SEG7DEC module included with this tutorial was generated by Synopsys' Design Compiler, which uses SEDIF.
Select the body of the SEG7DEC symbol and add the following property:

Name: FILEValue: seg7dec.sedif
Check and Save the symbol.

Now that a symbol exists for this component, you can instantiate it onto the top-level Calc schematic.
With the Calc schematic window active, click CHOOSE SYMBOL from the Schematic Palette and select the seg7dec component.
Instantiate this component between the ALUVAL(3:0) bus and the nets that lead to the outputs A-F as shown below.

Figure 10.5 Adding the SEG7DEC Symbol
Add the instance name SEGMENTS to the SEG7DEC symbol. (Add property INST, value SEGMENTS.)
Check and Save the Calc schematic. Leave the schematic open.

Extension	Netlist Format
.edif	Generic Xilinx-compatible EDIF 2.0
.xnf	Generic XNF (Xilinx Netlist Format) 6.x
.sedif	Synopsys Xilinx-compatible EDIF 2.0
.sxnf	Synopsys XNF 6.x

Linking a VHDL Entity to the ALU Component

VHDL can also be associated with a pre-existing symbol. The following procedure links the alu.vhd entity with the ALU symbol, which has already been instantiated on the Calc schematic.

As with SEG7DEC, ALU has a VHDL file, alu.vhd, that describes its behavior. In this exercise, you compile the alu.vhd file for simulation, link the compiled model to the existing ALU symbol, then update the instantiated entity in the Calc schematic so that it may be simulated and built into the implemented device.

Compiling the VHDL Entity

To compile the VHDL file for ALU, follow these steps.

Take a look at the alu or seg7dec.vhd file with the text editor you normally use.

This entity includes a four-bit data register, several multi-bit gate functions (AND, OR, and XOR), and an adder-subtractor. To model the device's system-wide global set/reset, an additional port, GBLRESET, has been added from the schematic-based ALU design. (See the “Schematic Design Tutorial” chapter.) This signal is brought into the process block that controls the four-bit data register:

VHDL ALU Register Description:
```
process (CLK, GBLRESET) 
   begin 
     if (GBLRESET='1') then 
       QIN <= "0000"; 
       OFL <= '0'; 
     elsif (CLK'event and CLK='1') then 
       if (CE='1') then 
         if (QRESET='1') then 
           QIN <= "0000"; 
           OFL <= '0'; 
         else
           QIN <= MUX; 
           OFL <= OVER;  
         end if; 
       end if; 
     end if; 
   end process;
```
The GBLRESET signal is written as an explicit asynchronous clear. This allows you to connect the registers in the ALU entity to the system-wide global-set/reset signal from the schematic. In an all-schematic design, the system-wide global-set/reset net does not need to be connected, since it is implicitly connected to all flip-flops in a device, both for simulation and implementation. For simulation purposes, however, this signal needs to be explicitly connected to all flip-flops in all VHDL modules. The Xilinx Core Tools recognize this as a redundant connection and subsequently trim it out of the implemented design.
When you are finished perusing the ALU VHDL description, close the file.

Since a work directory already exists for compiling VHDL modules, you can go directly to compiling the ALU entity.
Compile the src/alu.vhd file with the VCOM command:

vcom -explicit -qhpro_syminfo src/alu.vhd

The “-explicit” option allows VCOM to tolerate multiply-defined standard functions. This is required because the equality operator (“=”) is defined in both the ieee.std_logic_1164 and ieee.std_logic_unsigned packages, both of which are called out in the alu.vhd file.
With the Calc schematic still open in Design Architect, select the ALU symbol.
Open down into the symbol by selecting Right Mouse Button Open Down.
Select symbol:alu.
Click OK.

The Symbol Editor appears.

If you performed the Schematic Design Tutorial with the all-schematic-based Calc design, you should notice that the ALU symbol has an extra pin, GBLRESET, that corresponds to the extra VHDL port mentioned above.
From the menu bar, select File Import VHDL Entity.

The Import VHDL Entity dialog box appears.

Figure 10.6 Import VHDL Entity Dialog Box
Set the following values in the dialog box:

Table 10_4 Import VHDL Entity Settings for ALU

Field
Value

QVHDL InitFIle
$XILINX_TUTORIAL/calc_sot/modelsim.ini

Lib. Logical Name
work

Entity Name
seg7dec

Deflt. Architecture
[”behavior”, “QVHDL arch”, [“qvhpro”]]

NOTE
You can select the architecture setting from a list by clicking on the Choose Arch button. Since only one architecture has been compiled for the ALU entity, you may also leave this field blank.
Click OK.

In the Symbol Editor, the ALU symbol's body and pins are annotated with properties similar to those that Generate Symbol attached to the SEG7DEC symbol. These properties allow the underlying entity and the upper-level schematic portion to be simulated concurrently in QuickHDL Pro.

NOTE
If you get the error “Entity source work_library/_parsed.vhd does not exist,” make sure you specified the -qhpro_syminfo option on the VCOM command line.

Figure 10.7 ALU Symbol with VHDL-Import Properties
Since the ALU module is also a non-schematic element, you must attach a FILE property to it so the Xilinx netlister (NGDBUILD) can incorporate this portion of the design into the implemented netlist. The ALU netlist included with this tutorial was synthesized by Exemplar's Galileo Logic Explorer, and thus uses generic XNF.
Select the body of the ALU symbol and add the following property:

Name: FILEValue: alu.xnf
Check and Save the symbol.

Since the symbol has now changed, you must reflect the change in the top-level Calc schematic.
With the Calc schematic window active, select the ALU symbol, then select Right Mouse Button Update Auto.

This updates the ALU instantiation with the new symbol properties.

The GBLRESET pin on the ALU symbol must be attached to the global set/reset signal from the top-level design. This signal is the one connected to the GSR input on the STARTUP block. In the case of Calc, this net is also called GBLRESET.
Attach a new net to the GBLRESET pin and name it GBLRESET.

Figure 10.8 Updating the ALU Symbol
Check and Save the Calc schematic.
Exit Design Architect.