Functional Simulation

Pure HDL designs consist of a RTL VHDL or Verilog model. You can optionally convert the synthesis output netlist to a gate-level HDL model and functionally simulate it. The flow diagram for performing functional simulation on pure HDL designs is shown in the following figure.

Figure 4.3 Performing Functional Simulation on a Pure HDL Design

Pre-Synthesis Functional Simulation

To perform a pre-synthesis functional simulation on a pure HDL design follow these steps:

NOTE

This procedure assumes that you are using ModelSim. QuickHDL provides the same functionality as ModelSim. If you are using QuickHDL instead of ModelSim, see the “ModelSim and QuickHDL” appendix for details on how to modify this procedure.

1. Create a working library with vlib.
   
   vlib mywork
   
   
2. Map the library with vmap.
   
   vmap work mywork
   
   
3. If you are using LogiBLOX modules, use vmap to map to the compiled LogiBLOX modules location.
   
   vmap logiblox compiled_logiblox_area
   
   Your system administrator can tell you the location of the compiled version(s) of the LogiBLOX library. Instructions for compiling are in the Mentor Graphics Installation section of the Alliance Installation Guide. You may have to recompile the library for each version of ModelSim you use. The default directory for the compiled LogiBLOX library is as follows:
   
   $XILINX/mentor/data/vhdl/logiblox
   
   
4. If you are using Unified Library components, use vmap to map to the compiled Unified Library location by executing the appropriate line below for the device family that you are using.
   
   For vhdl:
   
   vmap unisim $XILINX/mentor/data/vhdl/unisim
   
   vmap unisim_5k $XILINX/mentor/data/vhdl/unisim_5k
   
   Map to unisim for the XC3000 and XC4000 series, or unisim_5k for the XC5200 series.
   
   For verilog:
   
   vmap uni3000 $XILINX/mentor/data/verilog/uni3000
   
   vmap uni4000x $XILINX/mentor/data/verilog/uni4000x
   
   vmap uni5200 $XILINX/mentor/data/verilog/uni5200
   
   Map to uni3000 for the XC3000 series, uni4000x for the XC4000 series, or uni5200 for the XC5200 series.
   
   

   ---

   NOTE

   The above locations for the compiled libraries are the default locations for a default software installation. However, your system administrator can install them in other locations. Your system administrator can tell you the location of the compiled version(s) of the Unified Library. Instructions for compiling are in the Mentor Graphics Installation section of the Alliance Installation Guide. You may have to recompile the library for each version of ModelSim you use.

   ---

5. Compile the HDL source files with vcom (VHDL) or vlog (Verilog).
   
   vcom [options] design_file(s)
   
   vlog [options] design_file(s)
   
   See the Mentor documentation for a description of the available options.
   
   
6. Compile your testbench with vcom (VHDL) or vlog (Verilog).
   
   vcom [options] testbench_file(s)
   
   vlog [options] testfixture_file(s)
   
   
7. Select the appropriate architecture configuration or module for your testbench and select ModelSim in the pld_dmgr tools window.
   
   See the Mentor documentation for ModelSim instructions.
   
   
8. After the RTL level simulation is correct, you may proceed to synthesis and to implementation or optional post-synthesis functional simulation.
   
   

Post-Synthesis Functional Simulation

To perform a post-synthesis functional simulation on a pure HDL design follow these steps:

NOTE

This procedure assumes that you are using ModelSim. QuickHDL provides the same functionality as ModelSim. If you are using QuickHDL instead of ModelSim, see the “ModelSim and QuickHDL” appendix for details on how to modify this procedure.

1. Create a working library with vlib.
   
   vlib mywork
   
   
2. Map the library with vmap.
   
   vmap work mywork
   
   
3. If you are using LogiBLOX modules, use vmap to map to the compiled LogiBLOX modules location.
   
   vmap logiblox compiled_logiblox_area
   
   Your system administrator can tell you the location of the compiled version(s) of the LogiBLOX library. Instructions for compiling are in the Mentor Graphics Installation section of the Alliance Installation Guide. You may have to recompile the library for each version of ModelSim you use. The default directory for the compiled LogiBLOX library is as follows:
   
   $XILINX/mentor/data/vhdl/logiblox
   
   
4. Since you are using Unified Library components, use vmap to map to the compiled Unified Library location by executing the appropriate line below for the device family that you are using.
   
   For vhdl:
   
   vmap unisim $XILINX/mentor/data/vhdl/unisim
   
   vmap unisim_5k $XILINX/mentor/data/vhdl/unisim_5k
   
   Map to unisim for the XC3000 and XC4000 series, or unisim_5k for the XC5200 series.
   
   For verilog:
   
   vmap uni3000 $XILINX/mentor/data/verilog/uni3000
   
   vmap uni4000x $XILINX/mentor/data/verilog/uni4000x
   
   vmap uni5200 $XILINX/mentor/data/verilog/uni5200
   
   Map to uni3000 for the XC3000 series, uni4000x for the XC4000 series, or uni5200 for the XC5200 series.
   
   

   ---

   NOTE

   The above locations for the compiled libraries are the default locations for a default software installation. However, your system administrator can install them in other locations. Your system administrator can tell you the location of the compiled version(s) of the Unified Library. Instructions for compiling are in the Mentor Graphics Installation section of the Alliance Installation Guide. You may have to recompile the library for each version of ModelSim you use.

   ---

5. Compile the HDL source files with vcom (VHDL) or vlog (Verilog).
   
   vcom [options] design_file(s)
   
   vlog [options] design_file(s)
   
   See the Mentor documentation for a description of the available options.
   
   
6. Compile your testbench with vcom (VHDL) or vlog (Verilog).
   
   vcom [options] testbench_file(s)
   
   vlog [options] testfixture_file(s)
   
   
7. Select the appropriate architecture configuration or module for your testbench and select ModelSim in the pld_dmgr tools window.
   
   See the Mentor documentation for ModelSim instructions.
   
   
8. After the post-synthesis simulation is correct, you may proceed to implementation.
   
   

Optional Post Synthesis Functional Simulation

You can optionally perform a post-synthesis functional simulation on a pure HDL design, by following these steps:

1. Run pld_edif2sim on your top-level EDIF or pld_xnf2sim on your top level XNF file from synthesis.
   
   
2. Specify either VHDL or Verilog output in the pld_edif2sim or pld_xnf2sim dialog box.
   
   
3. Choose the Flat or Hierarchical option and click OK to create the structural HDL netlist.
   
   

   Figure 4.4 Pld_edif2sim Dialog Box

   Figure 4.5 Pld_xnf2sim Dialog Box

4. Compile the HDL source file from pld_edif2sim or pld_xnf2sim.
   
   Note: Before compiling, if you have not already done so, verify that the VHDL or Verilog SIMPRIM libraries have been compiled. Before performing timing simulation on an HDL-based design, the VHDL or Verilog SIMPRIM libraries must be compiled with vcom/vlog. Your system administrator should have performed this during installation.
   
   The path to the VHDL libraries should be:
   
   $XILINX/mentor/data/vhdl/simprim
   
   The path to the Verilog libraries should be:
   
   $XILINX/mentor/data/verilog/simprim
   
   If these compiled SIMPRIM Libraries do not exist, contact your systems administrator. The Mentor Graphics Installation section of the Alliance Installation Guide describes how to compile the SIMPRIM libraries.
   
   

   ---

   NOTE

   The following two steps in this procedure assume that you are using ModelSim. QuickHDL provides the same functionality as ModelSim. If you are using QuickHDL instead of ModelSim, see the “ModelSim and QuickHDL” appendix for details on how to modify this procedure.

   ---

5. Use vmap to add a SIMPRIM library listing in the modelsim.ini file:
   
   vmap simprim compiled_simprim_library_directory
   
   The locations of the compiled simprim libraries (compiled_simprim_library_directory) are normally as follows:
   
   $XILINX/mentor/data/vhdl/simprim
   
   $XILINX/mentor/data/verilog/simprim
   
   
6. Type the following on the UNIX command line:
   
   vcom [options] design_name    (VHDL)
   
   vlog [options] design_name    (Verilog)
   
   See the Mentor documentation for information on how to use vcom and vlog.
   
   
7. Select the appropriate architecture configuration or module for your testbench.
   
   
8. After the post-synthesis simulation is correct, you may proceed to implementation.