Design Implementation

Once you complete functional simulation for HDL designs, you are ready to implement your design in an FPGA or CPLD. You perform implementation with the Xilinx Design Manager, a graphical design-flow and project manager. In the Mentor interface, the Xilinx Design Manager is called pld_dsgnmgr. You invoke pld_dsgnmgr from the Mentor Design Manager or from a UNIX shell.

The “HDL Design Implementation” figure shows the design flow for implementing a design. The Xilinx Design Manager accepts your design, represented by the XNF or EDIF file from the synthesis tool. Design entry of pure HDL designs, or HDL designs with LogiBLOX elements produces an EDIF or XNF file that you can submit to pld_dsgnmgr. Pld_dsgnmgr first translates the design into a flattened or hierarchical netlist, then optimizes, places, and routes the design. You can also use the Xilinx Design Manager to generate SDF timing information that you can import into ModelSim along with your VHDL or Verilog netlist. For a more in-depth discussion of the flow, including advanced implementation options, see the Development System User Guide.

Figure 4.6 HDL Design Implementation

To implement your design follow these steps:

1. Within the Mentor Design Manager, select the EDIF icon for your design in the Navigator, then select Right Mouse Button Open pld_dsgnmgr. The Xilinx Design Manager appears as shown in the “Xilinx Design Manager” figure. The tool automatically creates a Xilinx project called your_design_name. Xilinx project information is kept in a file called xproj/your_design_name.prj by default.
   
   

   Figure 4.7 Xilinx Design Manager

   Each project is associated with objects known as versions and revisions. Versions represent logic changes in a design (for example, adding a new block of logic, replacing an AND gate with an OR gate, or adding a flip-flop); revisions represent different executions of the design flow on a single design version, usually with new implementation options (for example, higher place and route effort, a change in part type, or experimentation with new bitstream options).
   
   
2. Within the Xilinx Design Manager, select Design Implement.
   
   The Implement dialog box opens as shown in the following figure and displays fields for part type, design version, and revision.
   
   

   Figure 4.8 Implement Dialog Box

3. The Xilinx Design Manager reads the part type from the design.
   
   If you wish to specify the part type manually, click the Select button to display a pull-down listing of available devices. Choose a family, a device, a package, and a speed grade. Click OK. The part number is inserted into the Part field in the Implement dialog box.
   
   
4. Click on Options. The Options dialog box appears as shown in the “Options Dialog Box” figure.
   
   

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   NOTE

   The CPLD Options dialog box does not have a Configuration Template section, nor does it have a Produce Logic Level Timing Report checkbox.

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   Figure 4.9 Options Dialog Box

5. Click the Browse button next to the User Constraints field. Select the appropriate .ucf file from the design directory, then Click OK.
   
   
6. Under Optional Targets, make sure the following are selected:
   
   
   • Produce Timing Simulation Data: This generates a SDF file and a VHDL or Verilog netlist that you can import into ModelSim.
     
     
   • Produce Configuration Data: This generates a programming bitstream suitable for downloading into the Xilinx device.
     
     
   • Produce Post Layout Timing Report: This generates a timing report file based on how the design is actually routed.
     
     You can also select the following option (FPGAs only):
     
     
   • Produce Logic Level Timing Report: This generates a preliminary (pre-place and route) timing report based on the number of logic levels in each signal path. Since it is generated before the place-and-route layout step, it does not contain information on device routing. Looking at this report before place and route can be useful for seeing how much routing slack you have in a design.
     
     
7. Select the Edit Template button on the right hand side of the Implementation field. The Implementation Options dialog box appears as shown in the following figure.
   
   

   Figure 4.10 Changing Simulation Data Option

8. Select the Interface tab. In the Interface pane, look under Simulation Data Options and verify that Format is set to VHDL or Verilog and that Correlate Simulation Data to Input Design is selected. The Vendor field should change to generic since these HDL outputs are not vendor specific.
   
   
9. Click OK to return to the Options window.
   
   
10. Click OK to return to the Implementation dialog box.
    
    
11. At this point you have the option to create a template testbench for the timing VHDL or Verilog netlist. To do so, perform these steps:
    
    
    1. In the Xilinx Design Manager, select Utilities Template Manager to open the Template Manager dialog box.
       
       

       Figure 4.11 Template Manager Dialog Box

    2. Select the implementation template that you wish to customize.
       
       
    3. Click on the Customize button to open the Customize dialog box.
       
       

       Figure 4.12 Customize Dialog Box

    4. If you have Verilog, specify ngd2ver in the Program Name box and -tf in the Program Options box.
       
       
    5. If you have VHDL, specify ngd2vhdl in the Program Name box and -tb in the Program Options box.
       
       
    6. Click Set and then OK.
       
       
    7. Click Close in the Template Manager dialog box.
       
       Whenever you output VHDL or Verilog with this customized implementation template, the testbench template file your_design.tvhd is created for VHDL designs and your_design.tv is created for Verilog designs.
       
       
12. The default hierarchy for VHDL or Verilog output files is flat since the write function and simulations are generally faster. At this point you have the option to retain the hierarchy to aid debugging. To do so, follow these steps:
    
    
    1. In the Xilinx Design Manager, select Utilities Template Manager to open the Template Manager dialog box as shown in “Template Manager Dialog Box” figure.
       
       
    2. Select the implementation template that you wish to customize.
       
       
    3. Click on the Customize button to open the Customize dialog box as shown in the “Customize Dialog Box” figure.
       
       
    4. If you have Verilog, specify ngd2ver in the Program Name box and -r in the Program Options box.
       
       
    5. If you have VHDL, specify ngd2vhdl in the Program Name box and -r in the Program Options box.
       
       
    6. Click Set and then OK.
       
       
    7. Click Close in the Template Manager dialog box.
       
       Whenever you output VHDL or Verilog with this customized implementation template, the testbench template file your_design.vhd is hierarchical for VHDL designs and your_design.v is hierarchical for Verilog designs.
       
       
13. In the Xilinx Design Manager Implement dialog box, specify the current version and revision you wish to work on, then click Run.
    
    

    Figure 4.13 Implement Dialog Box

    The Flow Engine opens as shown in the following figure.
    
    

    Figure 4.14 The Xilinx Flow Engine

    The status bar shows the progress of the implementation flow with the following stages:
    
    
    • Translate: Converts the design EDIF or XNF file into an NGD (Native Generic Design) file.
      
      
    • Map: Groups basic elements (bels) such as flip-flops and gates into logic blocks (comps). Also generates a logic-level timing report if desired.
      
      
    • Place&Route: Places comps into the device, and routes signals between them.
      
      
    • Timing: Generates timing simulation data and an optional post-layout timing report.
      
      
    • Configure: generates a bitstream suitable for downloading into and configuring a device
      
      When the implementation completes, an Implementation Status box appears with:
      
      Implementing revision ver1->rev1 completed successfully.
      
      
14. Click on View Logfile to display the logfile from Flow Engine.
    
    The report is displayed in vi.
    
    
15. To exit the viewer, type :q! and press Return.
    
    
16. Click OK in the Implementation Status dialog to return to the Xilinx Design Manager.
    
    

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    NOTE

    To use another text editor, such as Emacs, as the report viewer, select File Preferences from the Xilinx Design Manager.

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