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Timing Simulation

For HDL designs, the Xilinx Design Manager produces a V (Verilog) file or a VHDL file expressed in SIMPRIMs and a corresponding SDF file that contains the timing data. The SDF file for VHD and V files are not interchangeable since the models they annotate follow different modeling standards.

Compiling the SIMPRIM Libraries

Before performing timing simulation on an HDL-based design, the VHDL or Verilog SIMPRIM libraries must be compiled with vcom/vlog. Your system administrator should perform this during installation. Perform these steps:

  1. Verify that the libraries have been compiled.

    The path to the VHDL libraries should be:

    $XILINX/mentor/data/vhdl/simprim

    The path to the Verilog libraries should be:

    $XILINX/mentor/data/verilog/simprim

  2. If these compiled SIMPRIM Libraries do not exist, contact your systems administrator. The Mentor Graphics Installation section of the Alliance Installation Guide describes how to compile the SIMPRIM libraries.

Passing Timing Generics to Special Cells - ROC, OSC, OSC4, and OSC5

If your designs do not have an external global set or reset port or a user defined internal net driving the global set/reset net, then a ROC (Reset on Configuration) cell is automatically added to your VHDL netlist. This cell enables you to toggle the global set/reset net at the beginning of simulation by defining the pulse width of the signal pulse starting at time 0. By default, the pulsewidth is 0 which enables simulation to proceed but does not reset the circuit. To properly simulate the reset behavior of the chip, the pulse width generic should be set to a value within the range found in the Xilinx Databook for the particular device.

You can modify the following configuration for the technology's specific pulse width and user's testbench and compile it before you compile the testbench.

CONFIGURATION cfg_my_timing_testbench OF my_testbench IS 
    FOR my_testbench_architecture 
     FOR ALL:my_design USE ENTITY work.my_design(structure); 
      FOR structure 
       FOR ALL:roc USE ENTITY work.roc(roc)v) 
        GENERIC MAP ( width => 100 ms); 
       END FOR; 
      END FOR; 
     END FOR; 
    END FOR; 
   END cfg_my_timing_testbench;

Verilog designs do not require ports to drive the global/set reset net from a testbench. Therefore, Verilog designs do not contain the ROC cell. The same signal name found in the front end can be used to drive the signal in the back-annotated design. The signal must be driven, or all flip-flops will initialize as X.

VHDL designs that contain oscillator cells like OSC, OSC4, or OSC5, must have the clock period set with a configuration statement. By default, the period is 0, disabling the oscillator. You should carefully select the period from the range of viable periods found in the Xilinx Databook for the particular technology. A specific period is not guaranteed because the cell is subject to process variations. You should select the value that best meets your simulation requirements.

You can use the following configurations for either the OSC, OSC4, or OSC5 cells by just changing the name of the cell and modifying the pulse width to the correct value.

CONFIGURATION cfg_my_functional_testbench OF my_testbench IS 
    FOR my_testbench_architecture 
     FOR ALL:my_design USE ENTITY work.my_design(my_design_rtl); >
      FOR my_design_rtl 
       FOR ALL:my_submodule USE ENTITY work.my_submodule(my_submodule_rtl); 
        FOR my_submodule_rtl  
         FOR all: osc4 USE ENTITY work.osc4(structure)  
          GENERIC MAP ( period_8m => 125 NS); 
         END FOR; 
        END FOR; 
       END FOR; 
      END FOR;  
     END FOR; 
    END FOR; 
   END cfg_my_testbench_functional;

You can drive Verilog designs by the signal name used to drive the front-end simulation since the hierarchical name is preserved.

Compiling the Design

Before performing timing simulation on an HDL-based design, you must compile your VHDL or Verilog modules with vcom/vlog.

NOTE

This procedure assumes that you are using ModelSim. QuickHDL provides the same functionality as ModelSim. If you are using QuickHDL instead of ModelSim, see the “ModelSim and QuickHDL” appendix for details on how to modify this procedure.

  1. Create a map and working library with vlib and vmap.

    vlib time_sim_lib

    vmap work time_sim_lib

    You should compile to a different work library than the one used for functional simulation to avoid data integrity mishaps.

  2. Use VMAP to add a SIMPRIM library listing in the modelsim .ini file:

    vmap simprim compiled_simprim_area

    The locations of the compiled simprim libraries (compiled_simprim_area) are normally as follows:

    $XILINX/mentor/data/vhdl/simprim

    $XILINX/mentor/data/verilog/simprim

  3. Type the following on the UNIX command line:

    vcom [options] time_sim.vhd (VHDL)

    vlog [options] tim_sim.v (Verilog)

    Design_name is the name of the VHDL or Verilog file produced by the Xilinx Design Manager. See the Mentor Graphics documentation for information on the options available.

  4. Compile any required configurations for special cells like ROC (reset on configuration) or OSC (see the “Passing Timing Generics to Special Cells - ROC, OSC, OSC4, and OSC5” section in this chapter).

    vcom [options] configuration_file (VHDL)

    vlog [options] configuration_file (Verilog)

  5. Select the appropriate architecture configuration or module for your testbench and select ModelSim in the pld_dmgr tools window.

    See the Mentor documentation for ModelSim instructions.

This procedure creates HDL database files that you can submit to ModelSim.

Simulating the Design

Simulate with ModelSim using vsim. To include the timing information in the SDF file, invoke vsim with the -sdftyp option. Refer to the Mentor documentation for information on available options. To simulate a Verilog based design, invoke vsim with the -L simprim option to choose the Verilog simprim libraries models.

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