Retargeting the Design to a Different Family

The Unified Libraries allow you to retarget your designs from one device family to another if both your source and target designs only include symbols from the Unified Libraries. Since most of the symbols in the Unified Libraries have the same footprint and name from one device family to another, you can easily convert your designs across Xilinx device families.

The procedure described in the following section uses Xilinx's Convert Design utility in Design Architect to retarget your schematic. It allows you to change every reference of every design object in your design directory from the source design library to the target design library. In your target design, the symbols that are common to the source and target families maintain their relative location and pin position in the schematic. Pins on these symbols retain their connectivity to the nets they were attached to in the source design.

You must manually replace symbols that are not common to your source and target families with equivalent logic. For example, if a GCLK was used in an XC3000A design that is retargeted for use in an XC4000E device, you must manually replace the GCLK symbol with a BUFGP, BUFG, or BUFGS, which is the XC4000E equivalent of a GCLK.

NOTE

In the following procedures, XC4000 is used as the source design device family, and XC5200 is used as the target design device family. You can also retarget other device families.

To retarget a design to a different family, perform these steps:

1. Activate Design Architect by using either of the methods described in the “Invoking Design Architect” section of the “Schematic Designs” chapter. You do not have to open the schematic.
   
   
2. On Design Architect's desktop background (the area outside any schematic or symbol windows) press the right mouse button and select Convert Design.
   
   The dialog box shown in the following figure appears.
   
   

   Figure 7.1 Convert Design To New Technology Dialog Box

3. In the field asking “Select a group of designs from a list file?,” click on yes or no.
   
   
   • Click no if you want to retarget a single design. Convert Design utility traverses the hierarchy of a given schematic and converts the schematics of any hierarchical blocks found on the top-level schematic.
     
     
   • Click yes if you have a number of designs to retarget, and their names are contained in a file, one design per line. This file is useful if your design has many lower-level schematics.
     
     

     ---

     NOTE

     You can create a list file with the UNIX ls command. The ls command lists all the MGC components within a single directory, and the sed command strips the trailer from .mgc_compoennt.attr. The result is directed to the list file.

     ---

     ls *.mgc_component.attr |
     sed s/.mgc_component.attr//g > listfile
     
     
4. In the Enter Design Name field, enter the design name or the name of the file listing the designs to retarget.
   
   
5. In the Schematic Name field, enter the name of the schematic model.
   
   The default is Schematic.
   
   
6. Select the Verbose mode switch.
   
   
7. Leave the Check and Save Switch field set to its default setting, manual checking, to allow you to find Xilinx components that do not convert properly. Once you become familiar with Convert Design's operation, you can select this field to have Convert Design automatically check and save the schematic.
   
   
8. In the From technology field, type the name of the device family from which you are converting. This field is case-insensitive.
   
   
9. In the To Technology field, type the name of the device family to which you are converting. This field is case-insensitive.
   
   
10. If you want the results of the conversion saved to a log file, type the name of the log file in the Log File Name field. The default is log_file.
    
    
11. Set a beep to sound for every un-matched symbol.
    
    
12. Click on OK to start the conversion.