Setting Global Reset and 3-State Signals

The way you set Global Reset and 3-State signals depends on which part type you are using. The methods are described below.

FPGA Designs

Before you simulate an FPGA design, you must force the
//globalsetreset (XC4000E designs) or the //globalreset (XC5200 designs) or the //globalresetb (XC3000 designs); otherwise, the flip-flops and latches do not function correctly.

1. Select your design directory icon in the Navigator window and select Right Mouse Button Open pld_quicksim to enter the pld_quicksim simulator.
   
   
2. Select the File Open Sheet menu item to display the Design Architect schematic.
   
   
3. Select the Add Force menu from the pld_quicksim Stimulus palette.
   
   
4. Fill in the dialog box with the //globalsetreset signal name, 25 for the first time, and 1 for the first value; n for the second time, and 0 for the second value.
   
   It is recommended that you do not force signals at time 0. See Mentor's QuickSim user guide for details.
   
   The reset width emulates a power-on reset at the beginning of simulation. Globalsetreset is now forced High at n ns. If you want to reset the flip-flops after n ns, toggle the globalsetreset Low and High for the necessary pulse width specified in The Xilinx Programmable Logic Data Book.
   
   

The previous procedure is slightly different for XC4000 IOBs and 3-state I/O pins.

To set XC4000E/EX IOB flip-flops, follow these instructions:

1. Set the IOB flip-flops High or Low on power-up by using the INIT property on the IOB flip-flops.
   
   
2. To activate the signal and begin simulation, set globalsetreset by selecting the Add Force menu item from the pld_quicksim Stimulus palette.
   
   
3. Fill in the dialog box with the //globalsetreset signal name, 25 for the first time and 1 for the first value; n for the second time and 25 for the second value.
   
   It is recommended that you do not force signals at time 0. See Mentor's QuickSim user guide for details.
   
   N is the specified minimum reset pulse width for the given speed grade part of the design, specified in The Xilinx Programmable Logic Data Book.
   
   

XC4000E/EX parts have a global input state to make all output pins 3-state, which allows the isolation of the XC4000E/EX part in board test. To simulate the global 3-state signal, force the signal named
//globalthreestate High using the Add Force command. Forcing the signal High holds all chip I/Os in a high-Z (3-state) state until
//globalthreestate is forced to zero.

CPLD Designs

Before you simulate a XC7000 or XC9000 CPLD design, you must force the //prld, otherwise, the flip-flops do not function correctly.

1. Select your design directory icon in the Navigator window and select Right Mouse Button Open pld_quicksim to enter the pld_quicksim simulator.
   
   
2. Select the File Open Sheet menu item to display the Design Architect schematic.
   
   
3. Select the Add Force menu from the pld_quicksim Stimulus palette.
   
   
4. Fill in the dialog box with the //prld signal name, 25 for the first time, and 1 for the first value; n for the second time, and 0 for the second value.
   
   It is recommended that you do not force signals at time 0. See Mentor's QuickSim user guide for details.
   
   The reset width emulates a power-on reset at the beginning of simulation. If you want to reset the flip-flops after n ns, toggle the prld High and Low for the necessary pulse width specified in The Xilinx Programmable Logic Data Book.