Functional Simulation

Pure Schematic Designs

1. Create a viewpoint using pld_dve:
   
   pld_dve -s design_name technology [viewpoint_name]
   
   
2. Perform functional simulation with pld_quicksim:
   
   pld_quicksim design_name[/viewpoint_name]
   
   

Schematic Designs with XNF Elements

1. Create a symbol in pld_da for each XNF element in your design.
   
   
2. To the symbols, add the FILE property with the path name of the XNF file as the value.
   
   
3. Run pld_men2edif to convert the entire design into EDIF.
   
   
4. Run pld_men2sim on this EDIF file to create a design component that represents the entire design:
   
   pld_edif2sim edif_file component_name technology -m -eddm [-sd dir]
   
   Use -sd to search additional directories other than the one containing the source EDIF file to find supporting EDIF, NGO, or XNF files.
   
   
5. Perform functional simulation with pld_quicksim:
   
   pld_quicksim design_name[/viewpoint_name]
   
   

Schematic Designs with LogiBLOX Elements

Schematic designs with LogiBLOX elements already contain simulation models, so you only need to create a viewpoint, then simulate.

1. Create a viewpoint using pld_dve:
   
   pld_dve -s design_name technology [viewpoint_name]
   
   
2. Perform functional simulation with pld_quicksim:
   
   pld_quicksim design_name[/viewpoint_name]
   
   

Mixed Schematic and VHDL with Schematic-on-Top Designs

You can simulate the design either before or after you synthesize the HDL module.

Before Synthesis

Follow these steps to simulate your design before you synthesize it:

1. Compile the VHDL module into a work library. If using Mentor version B.2 and up, use -qhpro -syminfo when compiling, otherwise Generate Symbol in the Design Architect will fail.
   
   
2. Create a symbol for the HDL module with pld_da using File Miscellaneous Symbol.
   
   
3. The Generate Symbol dialog box opens as shown in the “Generate Symbol Dialog Box” figure.
   
   
4. In the Generate Symbol dialog box, choose Entity as the source and specify the library logical name, entity name, and default architecture.
   
   
5. Instantiate the symbol on the schematic.
   
   
6. Create a viewpoint using pld_dve:
   
   pld_dve -s design_name technology [viewpoint_name]
   
   
7. Run QuickHDL PRO to simulate the design by typing the following syntax:
   
   qhpro [options] design_name
   
   

   Figure 8.1 Generate Symbol Dialog Box

After Synthesis

To simulate your VHDL design after you synthesize it, follow these steps:

1. Synthesize the HDL module that is being included on the schematic, and create an EDIF file from that synthesis.
   
   
2. Create a symbol for the HDL module with pld_da.
   
   
3. If the synthesis output was an EDIF file, run pld_edif2sim to convert it to a Mentor EDDM single object:
   
   pld_edif2sim edif_file symbol_component_name technology
   {-m|-s} -eddm [-sd dir1 ... -sd dirn]
   
   Use -m if the synthesis was performed with a Mentor tool; use -s if the synthesis was performed with a Synopsys tool.
   
   
4. Perform functional simulation with pld_quicksim:
   
   pld_quicksim design_name[/viewpoint_name]
   
   Where design_name is the EDDM design created by pld_edif2sim.
   
   

HDL-at-Top Designs

EDDM models must be inserted in the top-level HDL file.

1. Create a work library.
   
   
2. Perform the following steps for any schematic based components that need to be included in the top level VHDL:
   
   
   1. Run pld_dve -s to create a viewpoint for each EDDM component.
      
      
   2. Make sure the EDDM has an underlying symbol associated with it. If not create one using pld_da Miscellaneous Generate Symbol. Specify Schematics as the source in the dialog box.
      
      
   3. Run gen_arch to create entity and architecture source files.
      
      
   4. Instantiate this component into the top-level VHDL file.
      
      
3. Compile the VHDL source files with vcom:
   
   vcom [options] design_name
   
   See the Mentor documentation for a description of the available options.
   
   
4. Run QuickHDL PRO to simulate the design by typing the following syntax:
   
   qhpro [options] design_name
   
   For a description of the QuickHDL PRO options, see the Mentor Graphics documentation.
   
   

Pure HDL Designs

1. Create a working library.
   
   
2. Compile the HDL source files with vcom:
   
   vcom [options] design_name
   
   See the Mentor documentation for a description of the available options.
   
   
3. Simulate the design by running ModelSim. Type the following syntax:
   
   vsim [options] [-lib_name] [primary [architecture [primary] ...]