Design Implementation

Schematic Designs (FPGA)

The procedure for implementing pure schematic designs, designs with XNF elements, designs with LogiBLOX elements, and mixed-model schematic-at-top designs is the same. Follow these steps:

1. Convert the EDDM design to EDIF format with pld_men2edif:
   
   pld_men2edif design_name technology [viewpoint_name]
   [-b bus_delimiter]
   
   
2. Submit the design to NGDBuild, which reads a file in EDIF or XNF format, reduces all the components in the design to Xilinx primitives, runs a logical design rule check on the design, and writes an NGD file as output.
   
   ngdbuild -p technology design_name
   
   For example:
   
   ngdbuild -p xc4000ex test -sd dir
   
   
3. Map the logic to the components in the FPGA by typing the following syntax:
   
   map design_name.ngd -p partname
   
   For example:
   
   map -p 4000EXHQ240-3 test.ngd
   
   
4. Place and route the design:
   
   par -w design_name.ncd design_name.ncd
   
   The first file is created by the MAP utility, and PAR creates the other one.
   
   For example:
   
   par -w test.ncd test.ncd (writes out test.ncd created by map)
   
   par -w test.ncd test_par.ncd (writes new file test_par.ncd)
   
   
5. Back-annotate the design:
   
   ngdanno design_name.ncd design_name.ngm
   
   
6. Convert the design to an EDIF file:
   
   ngd2edif -a -v mentor design_name.nga -w
   
   
7. Submit the design to pld_edif2tim, the Mentor EDIF netlist reader, which converts an EDIF netlist to a Mentor single-object EDDM file that can be submitted to pld_quicksim for timing simulation. Use this syntax:
   
   pld_edif2tim design_name.edn
   
   This step creates a design library, design_lib, containing the design on which you can perform timing simulation.
   
   

Schematic Designs (CPLD)

When using CPLDs, the procedure for implementing pure schematic designs, designs with XNF elements, and mixed-model schematic-at-top designs is the same. Follow these steps:

1. Convert the EDDM design to EDIF format with pld_men2edif:
   
   pld_men2edif design_name technology [viewpoint_name]
   
   
2. Submit the design to the CPLD fitter.
   
   cpld -p partname design_name [-sd dir]
   
   
3. Convert the design to an EDIF file:
   
   ngd2edif -a -v mentor design_name.nga -w
   
   
4. Submit the design to pld_edif2tim, the Mentor EDIF netlist reader, which converts an EDIF netlist to a Mentor single-object EDDM file that can be submitted to pld_quicksim for timing simulation. Use this syntax:
   
   pld_edif2tim design_name.edn
   
   This step creates a design library, design_lib, containing the design on which you can perform timing simulation.
   
   

HDL-at-Top Designs

1. Synthesize the HDL modules in your design, and create an EDIF or XNF file from that synthesis.
   
   
2. Convert the EDIF or XNF file to an NGD file by using ngdbuild:
   
   ngdbuild -p technology design_name
   
   For example:
   
   ngdbuild -p XC4000E test (where test is the root name for the EDIF or XNF file)
   
   

   ---

   NOTE

   Referenced Mentor EDDM models must have their corresponding EDIF files created and residing in the same directory where the top level EDIF or XNF file resides. If they reside in other directories, you must use the -sd option to specify additional directories to search for such files.

   ---

3. Map the logic to the components in the FPGA by typing the following syntax:
   
   map design_name.ngd -p partname
   
   For example:
   
   map -p 4000EXHQ240-3 test.ngd
   
   
4. Place and route the design:
   
   par -w design_name.ncd design_name.ncd
   
   The first file is created by the MAP utility, and PAR creates the other one.
   
   For example:
   
   par -w test.ncd test.ncd(writes out test.ncd created by map)
   
   par -w test.ncd test_par.ncd(writes new file test_par.ncd)
   
   
5. Back-annotate the design:
   
   ngdanno design_name.ncd design_name.ngm
   
   
6. Convert the design to an EDIF file:
   
   ngd2edif -a -v mentor design_name.nga -w
   
   
7. Submit the design to pld_edif2tim, the Mentor EDIF netlist reader, which converts an EDIF netlist to a Mentor single-object EDDM file that can be submitted to pld_quicksim for timing simulation. Use this syntax:
   
   pld_edif2tim design_name.edn
   
   This step creates a design library, design_lib, containing the design on which you can perform timing simulation.
   
   

Pure HDL Designs

1. Synthesize the HDL file, and create an EDIF or XNF file from that synthesis.
   
   
2. Convert the EDIF or XNF file to an NGD file by using ngdbuild:
   
   ngdbuild -p technology design_name
   
   For example:
   
   ngdbuild -p XC4000E test (where test is the root name for the EDIF or XNF file)
   
   

   ---

   NOTE

   Referenced Mentor EDDM models must have their corresponding EDIF files created and residing in the same directory where the top level EDIF or XNF file resides.

   ---

3. Map the logic to the components in the FPGA by typing the following syntax:
   
   map design_name.ngd -p partname
   
   For example:
   
   map -p 4000EXHQ240-3 test.ngd
   
   
4. Place and route the design:
   
   par -w design_name.ncd design_name.ncd
   
   The first file is created by the MAP utility, and PAR creates the other one.
   
   For example:
   
   par -w test.ncd test.ncd (writes out test.ncd created by map)
   
   par -w test.ncd test_par.ncd (writes new file test_par.ncd)
   
   
5. Back-annotate the design:
   
   ngdanno design_name.ncd design_name.ngm
   
   
6. Convert the design to an EDIF file:
   
   ngd2edif -a -v mentor design_name.nga -w
   
   
7. Submit the design to pld_edif2tim, the Mentor EDIF netlist reader, which converts an EDIF netlist to a Mentor single-object EDDM file that can be submitted to pld_quicksim for timing simulation. Use this syntax:
   
   pld_edif2tim design_name.edn
   
   This step creates a design library, design_lib, containing the design on which you can perform timing simulation.