Timing Simulation

Schematic Designs

The procedure for performing timing simulation on pure schematic designs, designs with XNF elements, designs with LogiBLOX elements, and mixed-model schematic-at-top designs is the same. Follow these steps:

1. Use pld_edif2tim to create a Mentor EDDM model.
   
   pld_edif2tim design_name.edn
   
   
2. Create a viewpoint using pld_dve:
   
   pld_dve -s design_lib/design technology [viewpoint_name]
   
   
3. Run pld_quicksim to perform the timing simulation by using the following syntax:
   
   pld_quicksim -cp design_lib/design_name
   
   This command brings up DVE for cross-probing.
   
   For example:
   
   pld_quicksim -cp test_lib/test
   
   
4. Cross-probe between the original design and the new design.
   
   
5. Open the Viewpoint that was used to create the original design EDIF netlist.
   
   
6. Open the schematic sheet in pld_dve.
   
   
7. Select the signals to trace in the pld_dve schematic.
   
   Pld_quicksim automatically creates a trace window and adds the selected signals to it. Use pld_dve's schematic sheet window as if it were the sheet in the pld_quicksim window.
   
   

Pure HDL Designs

You can create either an output EDIF file or output VHDL/Verilog file from the Xilinx Design Manager (or Xilinx core tool scripts).

EDIF Method

1. Submit the design to pld_edif2tim, which converts an EDIF netlist to a Mentor single-object EDDM file that can be submitted to pld_quicksim for timing simulation. Use this syntax:
   
   pld_edif2tim design_name.edn
   
   This step creates a design library, design_lib, containing the design on which you can perform timing simulation.
   
   
2. Create a viewpoint with pld_dve:
   
   pld_dve -s design_lib/design_name technology
   
   
3. Simulate the timing with pld_quicksim:
   
   pld_quicksim design_lib/design_name
   
   

VHDL/Verilog Method

1. Compile the HDL source files with vcom:
   
   vcom [options] design_name
   
   See the Mentor documentation for a description of the available options.
   
   
2. Simulate the timing with ModelSim:
   
   vsim options [-lib_name] [primary [architecture [primary] ...]