This section briefly describes the UNIX command-line syntax of the commands that activate the Mentor and Xilinx programs that you can use to process your designs manually. They are listed in alphabetical order.
CPLD is a C-shell script for fitting into the XC7000 and XC9000 families. For a description of the CPLD command syntax and options, see the CPLD Schematic Design Guide or run the CPLD command with no parameters.
Dsgnmgr, the Xilinx Design Manager, is Xilinx's design implementation tool.
The dsgnmgr syntax can take the following three forms:
dsgnmgr
dsgnmgr project
dsgnmgr -design design.edif
When you use the first form of the syntax, the Design Manager appears with no project loaded. A project in this context means a Xilinx project.
When you use the second form of the syntax, the Design Manager appears but with the specified project loaded or opened. The project is a fully specified file name with a .prj extension. It is a file created by the Design Manager and contains the project information for a Xilinx project.
When you use the third form of the syntax, the Design Manager finds the design. A design in this context is a netlist file such as an EDIF file. If the design does not already have a Xilinx project associated with it, the Design Manager creates a project and appears with this project loaded. If the design does already have a Xilinx project associated with it, the Design Manager appears with that project loaded.
Edif2ngd converts an EDIF 2 0 0 netlist to a Xilinx NGO file. The EDIF file includes the hierarchy of the input schematic. The output NGO file is a binary database describing the design in terms of the components and hierarchy specified in the input design file.
For a description of the edif2ngd syntax and options, see the Development System Reference Guide.
The Notepad editor is a full-featured, window-based text editor. It is only available in the graphical user interface of the Mentor tools.
Gen_Arch creates VHDL entity and architecture from a Mentor (EDDM) component.
For a description of the Gen_Arch syntax and options, see the Mentor Graphics documentation.
MAP is a Xilinx tool that maps the logic to the components in an FPGA design.
For a description of the MAP syntax and options, see the Development System Reference Guide.
NGDAnno is Xilinx's back-annotation utility.
For a description of the NGDAnno syntax and options, see the Development System Reference Guide.
NGDBuild reads a file in EDIF or XNF format, reduces all the components in the design to Xilinx primitives, runs a logical design rule check on the design, and writes an NGD file as output.
For a description of the NGDBuild syntax and options, see the Development System Reference Guide.
Ngd2edif converts a Xilinx NGD or NGA file to an EDIF 2 0 0 netlist.
For a description of the ngd2edif syntax and options, see the Development System Reference Guide.
PAR is Xilinx's place and route tool.
For a description of the PAR syntax and options, see the Development System Reference Guide.
Pld_da is Design Architect, a schematic editor configured for Xilinx designs. For a description of Design Architect, see the Mentor Graphics Design Architect Users Manual.
Pld_dve creates a simulation or custom viewpoint for a Xilinx design.
The pld_dve syntax is the following:
pld_dve [-s] design_name technology [viewpoint_name]
When pld_dve creates a simulation viewpoint - that is, when you use the -s option - and if the viewpoint contains COMP or FILE primitives, pld_dve removes these primitives, then creates a viewpoint that can be submitted to pld_quicksim.
Pld_edif2sim is a utility that converts a Mentor, Synopsys, or any other Xilinx compatible EDIF file into a Mentor EDDM single object, VHDL netlist, Verilog netlist, or NGO file.
The pld_edif2sim syntax is the following:
pld_edif2sim edif_file symbol_component_name | output_file_name technology {-s|-o|-m} {-eddm|-vhdl|-verilog|-ngo} {-hier|-flat} {-ignore_unexpanded} [-sd dir1 ... -sd dirn] [-help]
Pld_edif2tim is the Mentor EDIF netlist reader, which converts an EDIF netlist to a Mentor single-object EDDM file that can be submitted to pld_quicksim for timing simulation.
The pld_edif2tim syntax is the following:
pld_edif2tim edif_file [-r] [-help]
Pld_men2edif is the Mentor EDIF netlist writer, which creates a hierarchical EDIF netlist from a Mentor schematic design.
The pld_men2edif syntax is the following:
pld_men2edif design_name technology [viewpoint_name]
[-b 'delimiter'] -circular [-help]
Pld_quicksim is an interactive logic simulator that performs functional or timing simulation on your designs.
The pld_quicksim syntax is the following:
pld_quicksim [-cp] design_name[/viewpoint_name]
For a description of the other options available in pld_quicksim, see the Mentor Graphics QuickSim Users and Reference Manuals.
To enable cross-probing between front-end and back-end designs in timing simulations, specify -cp. In this case, the syntax is the following:
pld_quicksim -cp test_lib/test
Pld_xnf2sim is a utility that converts an XNF file to a Mentor EDDM single object, VHDL netlist, or Verilog netlist.
The pld_xnf2sim syntax is the following:
pld_xnf2sim top-level_xnf_file [-list listfile] symbol_component_name | output_file_name technology
{-ignore_unexpanded} [-s] {-eddm|-vhdl|-verilog}
{-hier|-flat} [-sd dir1 ... -sd dirn] [-help]
XNF file(s) submitted to pld_xnf2sim must represent the entire design, including the top-level IO ports (EXT statements). Feeding an XNF file that only represents one part of a design (with no IO pads) results in an invalid simulation model. You can use the following procedure to run functional simulation on a schematic design that consists of a partial XNF:
ModelSim (vsim), is Mentor's simulator for behavioral VHDL, Verilog, VHDL-based, and Verilog-based gate-level designs composed of Unified Libraries or SIMPRIM elements.
The ModelSim syntax is the following:
vsim options [-lib_name] [primary [architecture [primary] ...]
For a description of the ModelSim options, see the Mentor Graphics documentation.
This documentation assumes that you are using ModelSim. QuickHDL provides the same functionality as ModelSim. If you are using QuickHDL instead of ModelSim, see the “ModelSim and QuickHDL” appendix for details on how to use QuickHDL in place of ModelSim.
QuickHDL PRO (qhpro) is Mentor's simulator for mixed-model schematic, VHDL, and Verilog designs. It can invoke ModelSim to simulate HDL-based elements, or QuickSim to simulate gate-level schematics.
The QuickHDL PRO syntax is the following:
qhpro options design_name
For a description of the QuickHDL PRO options, see the Mentor Graphics documentation.
QuickPath performs a static and slack timing analysis on designs. For a description of the QuickPath syntax and options, see the Mentor Graphics documentation.
Vcom compiles the VHDL to be able to run ModelSim (vsim) simulator.
vcom [options] design_name
See the Mentor documentation for a description of the available options.
Vlog compiles the Verilog files to be able to run ModelSim (vsim) simulator.
vlog [options] design_name
See the Mentor documentation for a description of the available options.
SysArch is the System Architect, which creates system-level designs. For a description of the SysArch syntax and options, see the Mentor Graphics documentation.
Pld_sg invokes the Mentor schematic generator (SG), which creates a schematic from an EDDM model. You must have a Mentor schematic generator license in order to use this tool. Usage is as follows:
pld_sg [options] [viewpoint_path]
See the Mentor documentation for a description of the available options.
