Using a constraints file, you can supply constraints information in a textual form rather than putting it on a schematic. Sometimes this method is more efficient than putting constraints on a schematic.
It is necessary instruct the place and route software to read and apply the .ucf file when the Xilinx Design Manager reads the design. The procedure for doing this is detailed later in the “Using the Xilinx Design Manager” section.
The calc_4ke.ucf user constraints file which is supplied with this tutorial is shown below as an example of a constraints file. The constraints file syntax is the same for all device families. Since you only specified one pin location for one of the many inputs and outputs on the Calc schematic, you must use a constraints file to place the rest.
# CALC_4KE.UCF
# User constraints file for CALC, XC4003E-PC84
# If the F pin is not constrained on the schematic,
# remove the comment (#) from NET F LOC=P50;
NET SWITCH(7) LOC=P19;
NET SWITCH(6) LOC=P20;
NET SWITCH(5) LOC=P23;
NET SWITCH(4) LOC=P24;
NET SWITCH(3) LOC=P25;
NET SWITCH(2) LOC=P26;
NET SWITCH(1) LOC=P27;
NET SWITCH(0) LOC=P28;
NET A LOC=P49;
NET B LOC=P48;
NET C LOC=P47;
NET D LOC=P46;
NET E LOC=P45;
# NET F LOC=P50;
NET G LOC=P51;
NET OFL LOC=P41;
NET GAUGE(3) LOC=P61;
NET GAUGE(2) LOC=P62;
NET GAUGE(1) LOC=P65;
NET GAUGE(0) LOC=P66;
NET STACKLED(3) LOC=P57;
NET STACKLED(2) LOC=P58;
NET STACKLED(1) LOC=P59;
NET STACKLED(0) LOC=P60;
# Remove the NOTGBLRESET line if STARTUP
# is not used in the schematic
NET NOTGBLRESET LOC=P56;
