Completing the Calc Design

To complete the tutorial design, you need to add a few design objects to the Calc schematic using Design Architect.

If you need to stop the tutorial at any time, be sure to save your work as follows:

1. Select Check Sheet from the menu bar.
   
   A window appears containing the results of the design rule check.
   
   
2. After reviewing the contents of this window, close it and reselect the schematic window.
   
   

   ---

   WARNING

   It is important to check your design first before saving it.

   ---

3. Select File Save from the menu bar to save the design.
   
   
4. Before proceeding to the next part of this tutorial, close (quit) the Calc schematic window.
   
   
5. If a dialog box appears asking if you want to save any changes, choose NO.
   
   

Design Description

The top-level schematic of the Calc tutorial design has been created for you. Each of the blocks in the schematic, such as CONTROL or ALU, is linked to a second-level module that describes its logic. Additionally, any second-level module can contain another block that references a third-level drawing, and so on. This organization is known as a hierarchical structure.

In this tutorial, you add three symbols to the ALU block schematic to complete it. First, you create the ANDBLK2 and ORBLK2 symbols and their underlying schematics and then add them to the schematic. Additionally, you add the FD4RE symbol from the Unified Libraries to the ALU block. After the ALU block is finished, you add the STARTUP block to the top-level Calc schematic to tie the device's global reset network to a device pin. To complete design entry, you add a CONFIG block, which lists a set of instructions that dictate how the core tools should process the design.

The Calc design is a four-bit processor with a stack. The processor performs functions between an internal register and either the top of the stack or data input from external switches. The results of the various operations are stored in the register and displayed in hexadecimal on a seven-segment display. The top value in the stack is displayed in binary on a bar LED. A count of the items in the stack is displayed as a “gauge” on another bar LED.

The design consists of the following functional blocks:

• ALU - The arithmetic functions of the processor are performed in this block.
  
  
• CONTROL - The opcodes are decoded into control lines for the stack and ALU in this module.
  
  
• STACK - The stack is a four-nibble storage device. It is implemented using synchronous RAM in the XC4000E design. You can substitute the RAM4_9K module, which uses flip-flops, in place of the RAM16X4S macro in the STACK schematic to implement the stack in an XC9000 or other non-XC4000E device.
  
  

  ---

  NOTE

  If RAM4_9K is used in a non-XC9000 device, it must be retargeted using Convert Design.

  ---

• DEBOUNCE - This circuit debounces the “execute” switch, providing a one-shot output.
  
  
• SEG7DEC - This block decodes the output of the ALU for display on the 7-segment decoder.
  
  
• CLOCKGEN - This block uses an internal oscillator circuit in XC4000E devices to generate the clock signal. In XC9000 designs, it is replaced by an input pad and a clock buffer.
  
  

  ---

  NOTE

  The XC3000 and XC5200 FPGA families also have on-board oscillators. See the CLKGEN3K and CLKGEN5K components included in the calc_sch directory to see how the oscillators in these families are used.

  ---

• BARDEC - This block shows how many items are on the stack on a “gauge” of four LEDs.
  
  
• SWITCH7 - This block is a user-defined module consisting of seven input flip-flops used to latch the switch data.
  
  

Creating the ANDBLK2 Symbol

Opening a Symbol Window

1. Use the left mouse button to select Open Symbol in the Command Palette.
   
   
2. Type $XILINX_TUTORIAL/calc_sch/andblk2 in the Component Name box.
   
   
3. Select OK.
   
   A symbol editor window appears.
   
   

Creating the Symbol Outline

1. Zoom in until the grid space markers, represented by small crosses, are visible in the symbol window.
   
   
2. Select ADD RECTANGLE from the palette.
   
   
3. Position the cursor in the upper left corner of the symbol window and press the left mouse button.
   
   
4. While holding down the left mouse button, move the cursor diagonally to the opposite corner of the symbol window to draw a rectangle that is six grid squares high by eight grid squares wide. Be sure to measure using the grid marks, and not the small dots that define fractions of grid spacing.
   
   

Adding Pins to the ANDBLK2 Symbol

1. Select Add Pin from the palette.
   
   The dialog box in the following figure appears.
   
   
2. Fill in the Dialog box exactly as shown in the following figure and then select OK.
   
   

   Figure 9.6 Add Pin(s) Dialog Box for A(3:0) and B(3:0)

   A small crosshair appears under the cursor, and a rectangular box appears stating that the first pin, A(3:0), is to be placed.
   
   
3. Place pin B(3:0) as shown in the figure below by moving the cursor to the position where the diamond appears in the figure (one grid space to the left of the rectangle) and pressing the left mouse button. Small purple diamonds indicate pins.
   
   If you make a mistake before placing a pin, press the escape key to cancel the command, then repeat the above steps. If you make a mistake after placing a pin, press the F2 key to unselect everything. Select the pin (diamond) and the line next to it and press and hold CTRL-F2 to execute a move command. Move the pin to the correct position and release the keys.
   
   

   Figure 9.7 Adding Pins A(3:0) and B(3:0)

4. Select Add Pin from the palette and fill in the dialog box as shown in the following figure, then select OK. Be sure to set the name height to 1.0.
   
   

   Figure 9.8 Add Pin(s) Dialog Box for Q(3:0)

5. Place the pin Q(3:0) as shown in the figure below.
   
   
6. To adjust the positioning of the pin names, move the mouse over the text, press and hold the F7 function, and move the mouse to reposition the text. Release the F7 key to place the text at the new location.
   
   

   Figure 9.9 Adding Pin Q(3:0)

Adding Text

You can add comment text to a symbol to make it more easily identifiable on a schematic, or to annotate it without modifying its function. To add text to the symbol, perform the following steps:

1. Select the red TEXT button at the top of the palette to display the text editing icons.
   
   
2. Choose ADD TEXT from the palette.
   
   A small rectangular dialog box appears in the lower left portion of the window.
   
   
3. Type ANDBLK2 in the Text field of the dialog box, then press return or select OK.
   
   
4. Move the cursor into the symbol editor window and place the text directly above the symbol body by moving the mouse to the proper position and pressing the left mouse button.
   
   If you make a mistake while typing the text and the text has already been placed, move the mouse over the text and press the F7 key while holding down the shift key. A small dialog box appears at the bottom of the screen containing the selected text. Modify the text in the dialog box. Select OK to change the text on the symbol. You can use this method to modify any text on the symbol, such as pin names.
   
   

Modifying Text Size

To modify symbol text size, perform the following steps:

1. Press the F2 key to unselect everything.
   
   
2. Use the left mouse button to select the text, ANDBLK2, at the top of the symbol.
   
   
3. Select Right Mouse Button Change Height 1.5 X pin spacing.
   
   
4. Place the cursor over the text and press and hold the F7 key.
   
   
5. While still holding down the F7 key, move the text so that it is centered above the symbol body, as shown in the following figure.
   
   

   Figure 9.10 Completed ANDBLK2 Symbol

Saving the ANDBLK2 Symbol

To save the ANDBLK2 symbol, perform the following:

1. From the menu bar, select Check With Defaults.
   
   A text window appears containing the results of the design rule check.
   
   
2. Check to see that the information displayed is the same as that in the following figure. If you do not have the same output, correct the symbol to eliminate the differences and then check the symbol again.
   
   

   Figure 9.11 Output from Check

3. Close the text window by selecting Close from the menu that appears when the left mouse button is pressed in the box in the upper left hand corner of the text window.
   
   
4. Select File Save Symbol from the menu bar to save the symbol.
   
   

Creating the ORBLK2 Symbol

The next step is to create the symbol for ORBLK2, as shown in the following figure. Since ORBLK2 is similar to ANDBLK2, use the ANDBLK2 symbol and modify the text as described below.

1. Move the cursor above the ANDBLK2 text.
   
   
2. Press the F7 key while holding down the shift key to select the Change Text Value command.
   
   
3. In the small dialog box that appears in the lower left corner, type ORBLK2 in the New Text field, then select OK.
   
   

   Figure 9.12 Completed ORBLK2 Symbol

4. If necessary, use the cursor and F7 key to move and center the text, as described earlier.
   
   
5. From the menu bar, select Check With Defaults.
   
   A text window appears containing the results of the design rule check. Since you are modifying the ANDBLK2 symbol, the text still refers to ANDBLK2.
   
   
6. If any errors are reported in the Check text window, correct them on the symbol and check the schematic again. Otherwise, close the text window.
   
   
7. To save the symbol as ORBLK2, select File Save Symbol AS.
   
   A dialog box appears.
   
   

   ---

   WARNING

   It is important that you select the Save Symbol As command instead of Save to prevent overwriting the original ANDBLK2 file.

   ---

8. Enter $XILINX_TUTORIAL/calc_sch/orblk2 in the component name field and enter orblk2 in the interface name field.
   
   
9. Select OK to execute the command.
   
   This saves the symbol as ORBLK2.
   
   
10. Close the window containing the symbol.
    
    A dialog box appears prompting you to save the changes to ANDBLK2. Since the symbol for ANDBLK2 was saved prior to modifying it for the ORBLK2 symbol, it is not necessary to save changes to the ANDBLK2 symbol.
    
    
11. In the dialog box, select No.
    
    

Creating Schematics for ANDBLK2 Symbol

You have created symbols for ANDBLK2 and ORBLK2. The next step is to create schematics for these blocks. You can then reference the schematics in a higher-level schematic by placing the symbols.

Opening a Schematic Window

1. To open a schematic window, select OPEN SHEET from the palette.
   
   
2. In the dialog box that appears, type $XILINX_TUTORIAL/calc_sch/andblk2 in the Component Name field.
   
   
3. Select OK.
   
   A blank schematic sheet appears.
   
   

Adding the First Component to a Schematic

1. From the menu bar, select Libraries XILINX Libraries.
   
   The Xilinx Libraries menu appears.
   
   
2. Use the Unified Libraries for new designs. The Obsolete Library is provided for backward compatibility. Select Unified Lib from the menu.
   
   
3. Select the correct library for the device you are targeting, either XC4000E or XC9000.
   
   If you select the wrong library, use the PageUp key to go to the top of the Library Palette menu and click the left mouse button on the Back option. This moves the library menu back up the hierarchy.
   
   
4. Choose BY TYPE from the palette.
   
   This option organizes the library parts into categories. The ALL PARTS option displays all the library parts at once. A menu appears similar to that shown in the figure below.
   
   

   Figure 9.13 XC4000E Library BY TYPE Menu

5. To move up and down in the menu, turn on the scroll bars by moving the cursor into the menu window and selecting Right Mouse Button Show Scroll Bars. You can also move up and down using the PageUp and PageDown keys.
   
   
6. Click the left mouse button on the Set As Default option. This option allows you to return to this area and view of the library menu by clicking on the Library icon in the Schematic Palette.
   
   
7. Choose the logic category from the BY TYPE menu.
   
   
8. Select and2.
   
   
9. In the small dialog box that appears on the screen, move the cursor into the schematic window.
   
   The outline of a 2-input and gate appears.
   
   
10. Move the symbol outline to the location shown in the following figure and then click the left mouse button to place the object.
    
    

    Figure 9.14 Placing a Component

Placing Additional Components

After placing the and2, note that a picture of it appears in the small window in the upper right area of the screen. The last library element selected appears in this window.

1. To select another component of the same type, move the mouse inside this window, and click the left mouse button.
   
   
2. Then move the cursor to the schematic window, position the component, and release the mouse button to place it on the sheet.
   
   
3. Using this method, select and place a second and2 symbol as shown in the following figure.
   
   

   Figure 9.15 Placing a Second Component

Copying a Component

Use the Copy command to add more components by copying a component that already appears on the schematic.

1. Press the F2 function key to ensure that nothing is selected.
   
   It is important to use the F2 key before selecting objects because objects selected in previous steps are sometimes not deselected.
   
   
2. Move the mouse above and to the left of the two symbols on the sheet.
   
   
3. While holding down the left mouse button, move the mouse below and to the right of the two symbols.
   
   A white box appears surrounding the two symbols.
   
   
4. Release the mouse button to select the objects.
   
   
5. Select Right Mouse Button Copy. Alternatively, use stroke 3214789, a stroke in the form of a “C”, to select the copy command.
   
   A small dialog box appears at the bottom of the screen.
   
   
6. Place the two copied gates above the original two using the left mouse button. If necessary, use the 753 stroke to zoom out.
   
   The dialog box disappears after you place the gates.
   
   
7. Press Shift - F8 to view the entire schematic.
   
   The schematic now looks like the following figure.
   
   

   Figure 9.16 Component Placements for ANDBLK2

Moving a Component

If you make a mistake when placing a component, you can use the menu commands to move the component.

1. Use the F2 key to deselect.
   
   
2. Select the component by clicking on it with the left mouse button.
   
   The component appears highlighted, indicating that it has been selected.
   
   
3. Select Right Mouse Button Move, or use the stroke 74159.
   
   A small dialog box appears.
   
   
4. Click the left mouse button to correctly place the component.
   
   The dialog box disappears after the component is placed.
   
   

Adding Buses to a Schematic

Sometimes it is convenient to draw a set of signals as a bus rather than as several separate wires. It is not necessary to physically connect a bus to the nets that make up the bus. There are several schematics in the Calc design that have short bus segments that are not connected to anything. This is done so that a bus pin can be used to represent the bus on the symbol. A bus must exist on the schematic if a bus pin is to be used for a set of signals.

Add buses to the schematic as follows:

1. After pressing the F2 key, select Right Mouse Button Bus.
   
   A small dialog box appears, and a white cross appears under the cursor.
   
   
2. Draw a bus by clicking the left mouse button to specify the starting point, moving the mouse to a new position, and then clicking the button again to make a bend in the bus or to connect it to a pin. Terminate the bus is by clicking the mouse button in the same place twice. Add the three buses shown in the figure below. You may want to zoom the schematic view out before performing adding the buses.
   
   If you make a mistake, press the F2 key to deselect everything on the sheet. Then click on the bus segments you want to delete so that they appear highlighted. Press the Delete key and then redraw them correctly.
   
   
3. After adding the three buses, press the Escape key to exit the bus adding mode.
   
   

   Figure 9.17 ANDBLK2 Schematic with Buses

Adding Nets to a Schematic

Next, nets must be added to attach the appropriate pins on the gates to the buses. You may want to enlarge the view of the components to make it easier to draw the nets.

1. Press the F2 key.
   
   
2. Select Right Mouse Button Wire from the ADD menu.
   
   A small dialog box appears, and a white cross appears under the cursor.
   
   

   ---

   NOTE

   If the ADD menu does not appear, it may be that something is still selected, resulting in a different menu appearing on the screen. If this happens, press the F2 key and repeat step one.

   ---

3. Move the cursor to the top input pin of the top and2 gate, then click the left mouse button.
   
   
4. Move the cursor to the left, so that the pointer is laying atop the leftmost bus. (The wire should form a ninety-degree angle with the bus.) Click the left mouse button twice to terminate the wire.
   
   

   Figure 9.18 Connecting a Net

   A bus ripper is inserted automatically between the wire and the bus as shown in the “Connecting a Net” figure. A bus ripper defines which bit of the bus is connected to the wire. Automatically inserting bus rippers is referred to as autoripping.
   
   If the bus ripper did not automatically get inserted, make sure that you clicked on the pin first and then on the bus to attach a net between the two. If the net is attached to the bus first, autoripping does not occur. Also, check the Setup menu to make sure that autoripping is turned on. “Set Autoripping Off” should be displayed in the menu to indicate that autoripping is turned on. If “Set Autoripping On” is displayed, select it to turn autoripping on. Also, the $MGC_GENLIB environment variable must be set correctly for the autoripping function.
   
   A dialog box as shown in the “Label Bus Dialog Box” figure below appears. This box allows you to label a net which has a bus ripper connected to it. Labeling is the process of identifying a net or a component by assigning a text string to it. It is recommended that you label all nets on the schematic, to simplify debugging and simulation. To specify the bus signals they are related to, all nets that are attached to buses must have a number in parentheses at the end of their names. For example, a net that is bit zero of bus A must be labeled A(0).
   
   

   Figure 9.19 Label Bus Dialog Box

   Fill out the fields as shown in this example, so that this first net is labeled A(0). Note that you can label the bus as well as the net, but you will do this later.
   
   If the dialog did not appear as shown, choose SETUP RIPPER from the palette and make sure that Ripper Mode is set to “Implicit” and that Ripper Query is set to “On”. After setting these parameters, select OK, then delete the net and start again from step one.
   
   
5. After filling out the dialog box, you are asked to place the net label, or net name, on the schematic. Place the label as shown in the following figure and click the left mouse button.
   
   

   Figure 9.20 Adding and Placing a Net Name

6. Press the Escape key to exit the wire-adding mode.
   
   

Completing the Net Connections

Add the remaining nets to the schematic as follows:

1. Press the F3 key to execute the Add Wire command, or use the downward stroke 258.
   
   
2. Add the remaining nets as shown in the “ANDBLK2 with All Wires and Buses Connected” figure below.
   
   

   ---

   NOTE

   When a wire is properly attached to a symbol pin, the small diamond that specifies the connection point for the pin disappears. If any of the diamonds are still visible, delete the associated net and reattach it.

   ---

   Figure 9.21 ANDBLK2 with All Wires and Buses Connected

Increasing Text Size

At this point, all nets in the ANDBLK2 schematic have been labeled. However, the text of these labels is quite small compared to the other elements in the schematic.

To make the labels more readable:

1. Select all nets in the design by dragging with the left mouse button over the A(x) and B(x) nets then releasing, then doing the same with the Q(x) nets. In each case, a selection marquis appears as shown in the “Selecting Nets” figure. This is an additive selection; elements selected previously remain selected. Note that the marquis need only touch elements you wish to select; it need not enclose these elements completely.
   
   

   ---

   NOTE

   If you accidently select any elements besides the nets (bus rippers, buses, or gates), press F2 to unselect everything, then repeat the selection procedure.

   ---

   Figure 9.22 Selecting Nets

2. To change the size of the net labels, choose Right Mouse Button Properties Change Text Height 1.0 x Pin Spacing.
   
   
3. In the Change Property Height dialog box that appears as shown below, type NET in the Property Name field as indicated to increase the height of all NET properties on all selected elements.
   
   

   Figure 9.23 Increasing Text Size

   All net and bus labels are attached as a property called “NET” with a value equivalent to the net or bus label.
   
   The label sizes are increased as shown in the figure below.
   
   

   Figure 9.24 Schematic with Larger Net Names

Adding Ports

You must add port symbols to nets and buses to define the connectivity between a schematic and its associated symbol. For the ANDBLK2 schematic, all three buses need ports. Input signals are given PORTINs and output signals are given PORTOUTS.

Add ports to the schematic as follows:

1. If the appropriate Unified library is not displayed in the palette, use the menu bar command Libraries XILINX Libraries to select it. Select the Unified Libraries and the appropriate library for the part being used.
   
   
2. If the library is already visible, you may need to choose the BACK option from the top of the Library Palette to move up to the general library categories. Continue selecting BACK until the ALL PARTS and BY TYPE selections are displayed.
   
   
3. Select BY TYPE, and then choose the io category.
   
   
4. Select the portin library part from the menu.
   
   
5. Place the portin so that the white crosshair is exactly above the left end of the upper input bus, on the left side of the window.
   
   
6. Place another portin at the end of the lower input bus, on the left side of the window.
   
   
7. Select a portout symbol from the library and place it at the end of the output bus.
   
   
8. Press Shift-F8 to view the entire schematic.
   
   The schematic appears as in the following figure.
   
   

   Figure 9.25 Adding Ports

Labeling Ports

Normally, you label nets and buses by selecting them, then executing the menu selection Right Mouse Button Name Nets as shown later in this tutorial. However, the addition of the port symbols to the buses has automatically assigned a default name of “NET” to each bus. This simplifies the process since you can modify the existing names rather than add new ones.

1. Press the F2 key to unselect everything on the schematic sheet.
   
   
2. Move the cursor so that it sits above the NET label on the output bus.
   
   
3. Press Shift-F7 to choose the Text Change Value command.
   
   A small dialog box appears.
   
   
4. In the New Value field, change the text to Q(3:0).
   
   
5. Press return or choose OK in the dialog box.
   
   
6. Repeat this procedure on the two remaining buses, giving them names as shown in the following figure.
   
   

   Figure 9.26 Labeling Buses

Saving the Schematic

The schematic is now complete. Check and save the schematic as follows:

1. Select Check Sheet.
   
   The text window that appears should not contain any warnings about unnamed or dangling net vertices, since all pins in the schematic should be connected.
   
   
2. If these or any other warnings or errors occur, recheck the schematic against the following figure.
   
   

   Figure 9.27 Completed ANDBLK2 Schematic

   The check sheet window is also linked to the schematic window. Any net, vertex, or instance names can be highlighted in the check sheet window by clicking the left mouse button on it. The corresponding net, vertex, or instance on the schematic is highlighted. This is useful for relating an error message in check sheet to the schematic.
   
   
3. Once all schematic errors have been corrected, check the design again if necessary, and close the check sheet text window.
   
   
4. Select File Save Sheet from the menu bar to save the schematic.
   
   

Creating Schematics for ORBLK2 Symbol

The ORBLK2 schematic is similar to the ANDBLK2 schematic. To create schematics for the ORBLK2 symbol, you can use the ANDBLK2 schematic and simply replace the four and2 gates with or2 gates as described in the following procedure.

1. Press the F2 key to unselect everything on the ANDBLK2 schematic.
   
   
2. Display the BY TYPE library menu and select the logic category.
   
   
3. Press and hold the left mouse button and move the mouse to create a rectangle to include part of all four and2 gates, as shown in the following figure. It is not necessary to box the entire gate to select it. Do not include any part of the attached nets in the rectangle.
   
   

   Figure 9.28 Selecting Gates

4. When the rectangle is positioned correctly, release the left mouse button to select all four and2 gates.
   
   
5. Select Right Mouse Button Replace From Library Menu.
   
   A message appears at the bottom of the screen requesting that you select the replacement library part from the menu.
   
   
6. Use the PageUp and PageDown keys to scroll the component list. Select the or2 component.
   
   The four and2 gates are replaced with or2 gates. The ORBLK2 schematic is complete.
   
   
7. Select Check Sheet from the menu bar.
   
   The check program refers to the ANDBLK2 schematic, since this was modified to create the ORBLK2 schematic.
   
   
8. Close the text window containing the results of check sheet.
   
   
9. Select File Save Sheet As.
   
   
10. In the dialog box that appears, type $XILINX_TUTORIAL/calc_sch/orblk2 in the Component name field and leave all other fields blank.
    
    
11. Press return to save the schematic.
    
    

    Figure 9.29 Completed ORBLK2 Schematic

Editing the ALU Schematic

So far you have created symbols for ANDBLK2 and ORBLK2. You have also created underlying schematics for these symbols. The next step is to place the symbols in the ALU block schematic.

1. Close the only open window, which is the modified ANDBLK2 schematic, using the button in the upper left corner of the window.
   
   
2. In the dialog box that appears asking whether to save the changes to the schematic, select No, since the ANDBLK2 schematic was saved earlier, but then modified for use as the ORBLK2 schematic.
   
   
3. Choose OPEN SHEET from the Session Palette.
   
   
4. Press the Navigator button to open a Navigator window.
   
   
5. If necessary, change directories to the $XILINX_TUTORIAL/calc_sch directory using the up arrow to move up one directory level and double-clicking folders to push into them. Then, select the Calc design, which is represented by a folder with a “c” on it and with the name “calc” next to it. The “c” specifies that it is a component, and not just a directory.
   
   
6. Press return or select OK from the Navigator window.
   
   The Component Name field of the OPEN SHEET dialog box is automatically back-filled with “$XILINX_TUTORIAL/calc_sch/calc”.
   
   
7. Press return or select OK from the OPEN SHEET dialog box. The top level Calc design appears in a window. Press Shift - F8 to view the entire schematic, if necessary.
   
   
8. Press F2 key to unselect everything on the schematic.
   
   
9. Select the ALU symbol.
   
   
10. The additions you need to make are all in the ALU schematic, so choose File Open Down from the menu bar using the left mouse button.
    
    The Open Down dialog box appears as shown in the following figure.
    
    

    Figure 9.30 Open Down Dialog Box

11. In the Open Down dialog box, specify whether to modify the symbol or the schematic for ALU by selecting schematic sheet1, with the left mouse button. The selected line appears highlighted in the dialog box.
    
    
12. Press return or select OK.
    
    A second schematic window appears containing the ALU schematic.
    
    

Placing User-Created Components

You can now place the ANDBLK2 and ORBLK2 symbols on the schematic as shown in the figure below. You place the symbols using the same procedure you used to place the and2 gate from the Xilinx libraries when you created the ANDBLK2 schematic.

1. Use the F8 key to zoom into the empty area near the center of the schematic, between the XORBLK2 and ADSU4 symbols.
   
   
2. Press the F2 key to ensure that nothing is selected.
   
   
3. Choose Right Mouse Button Instance Symbol by Path.
   
   In the Add Instance dialog box that appears, use the Navigator button to select the $XILINX_TUTORIAL/calc_sch/andblk2 component, or type the name in the Component Name field.
   
   
4. Press return or select OK to execute the command.
   
   
5. Move the cursor to the correct location as shown in the following figure.
   
   

   Figure 9.31 Adding ANDBLK2 and ORBLK2 to ALU Schematic

6. Press the left mouse button to place the component.
   
   
7. Follow the same procedure to add the ORBLK2 symbol. Refer to the ALU schematic in the figure above for proper placement.
   
   
8. If you make a mistake when placing a component, select it (after pressing F2 key) and use Right Mouse Button Move to reposition it.
   
   

Placing Library Components

The next step in the tutorial is to add the fd4re and and5b2 components to the ALU schematic. The fd4re component is available in the Xilinx Unified Libraries and consists of four flip-flops with a clock enable. The and5b2 component is a five-input AND gate with two inputs inverted (“bubbled,” hence the “b”).

NOTE

These components are available in all libraries, including those for the XC4000E and XC9000.

1. Use the Shift -F8 keys to display the entire ALU schematic.
   
   
2. Use the F8 key to zoom into the open area in the lower right-hand corner.
   
   
3. Select Libraries XILINX Libraries from the menu bar.
   
   
4. Select the Unified Libraries and the appropriate family library using the left mouse button.
   
   
5. Choose BY TYPE flip_flop fd4re from the Library menu.
   
   
6. Move the cursor into the schematic window.
   
   An outline of the fd4re component appears.
   
   
7. Move the component to lower right corner of the schematic, approximately to the location shown the “Adding FD4RE and AND5B2 to ALU Schematic” figure.
   
   
8. Press the left mouse button to place the component.
   
   
9. Repeat steps two through six to place the and5b2 component next to the fd4re as shown in the figure below.
   
   When choosing the component from the library menu, use the selection BY TYPE logic and5b2.
   
   

   Figure 9.32 Adding FD4RE and AND5B2 to ALU Schematic

Adding Nets, Buses, Ports and Labels

FD4CE and AND5B2

Next, complete adding the fd4re and and5b2 symbols by adding nets, buses, and labels as follows:

1. Add the necessary nets and buses to complete connections for fd4re and and5b2 as you did for the previous schematic.
   
   The figure below displays the labeled nets and buses for fd4re and and5b2.
   
   
2. Add ports to the nets and buses attached to the fd4re and and5b2, as shown in the figure below.
   
   
3. Change the default “NET” properties to the proper names using the Shift-F7 key, as shown in the following figure.
   
   
4. To add net labels to nets not connected to ports or buses, select the nets as described earlier, then select Right Mouse Button Name Nets.
   
   For each selected net, the schematic editor asks you for a net label, then offers you the opportunity to place each label on the schematic. The nets should be labeled as shown.
   
   
5. Increase the size of the label text as described earlier.
   
   

   Figure 9.33 Nets, Buses, and Ports for FD4RE and AND5B2

ANDBLK2 and ORBLK2

Next, complete the addition of ANDBLK2 and ORBLK2 to the ALU schematic.

1. Add the necessary buses to complete connections for ANDBLK2 and ORBLK2. The figure below displays the labeled nets and buses for ANDBLK2 and ORBLK2.
   
   
2. Use the figure below to name the added buses by using the same Right Mouse Button Name Nets from the previous section. You only need to label the output buses of the two components, since the inputs to these components are connected to pre-labeled buses.
   
   

   Figure 9.34 Nets, Buses and Labels for ANDBLK2 and ORBLK2

Adding Labels to Components

It is important to add labels to components. Error and warning messages often reference component labels, and labels also appear in simulation netlists. Also, net names at lower levels of hierarchy are referenced using the following format:

...component_label/component_label/net_label

In the ALU schematic, labels have already been added to the MUXBLK2, XORBLK2, and MUXBLK5 blocks.

To add a label to the ANDBLK2 placement, follow these steps.

1. Press the F2 key to unselect everything.
   
   
2. Use the left mouse button to select the ORBLK2 symbol.
   
   
3. Select Right Mouse Button Properties Add.
   
   A dialog box appears.
   
   
4. In the window labeled “Existing Property Name”, choose the INST property with the left mouse button. It appears highlighted.
   
   
5. In the Property Value field, type ORBLK2, then press return or choose OK.
   
   
6. Move the text to position it as shown in the following figure and click the left mouse button to place the text.
   
   
7. Label the ANDBLK2 symbol the same way using the label ANDBLK2, as shown in the following figure.
   
   
8. Give the FD4RE component the label ALUVAL.
   
   

   Figure 9.35 Adding Component Labels to ALU Schematic

The completed ALU schematic is shown in the following figure.

Figure 9.36 Completed ALU Schematic

Saving the ALU Schematic

Check the schematic. If errors occur, resolve them and then check and save the schematic.

Exploring Xilinx Library Elements

The Xilinx libraries contain three types of elements. Primitives are basic logic elements such as the and2 and or2 gates that you previously placed in ANDBLK2 and ORBLK2. Soft macros are schematics created by combining primitives and other soft macros. Relationally Placed Macros (RPMs) are soft macros that contain placement information. RPMs are currently only available in the XC4000E library.

All three types of library elements are placed on a schematic in exactly the same way.

Viewing a Xilinx Soft Macro Schematic

Soft macro schematics are schematics such as you might make for your own designs. In fact, you can load one of these schematics and use the File Save As command to save it under another name, and then edit this new schematic to customize it to your needs.

Open the schematic underneath the fd4re symbol as follows:

1. Press the F2 key to unselect everything.
   
   
2. Select fd4re with the left mouse button.
   
   
3. Select File Open Down from the menu bar.
   
   
4. In the dialog box that appears, select the schematic sheet and click OK.
   
   As shown in the following figure, fd4re consists of four fdre symbols.
   
   

   Figure 9.37 FD4RE Schematic from XC4000E Library

Viewing a Xilinx RPM (XC4000-Based Families Only)

NOTE

The following description of RPMs contains detailed information on the XC4000E architecture. Refer to The Programmable Logic Data Book for more information on the XC4000E CLB structure and fast carry logic.

If your design is not targeted for the XC4000E family, read this section, but do not perform any of the commands. Continue the tutorial with the “Opening the Calc Schematic” section (the next section).

NOTE

The XC5200 library also contains RPMs. If you have an XC5200 schematic, you may open the ADSU4 component as described here to see how this RPM is implemented in that family.

The ALU contains a component from the Xilinx library, adsu4, which is a four-bit wide adder/subtracter. If your design is targeted for the XC4000E library, this schematic is implemented as a Relationally Placed Macro (RPM). If your design is not targeted for the XC4000E or XC4000EX library, adsu4 is implemented without this placement information.

RPM schematics are schematics such as you might make for your own designs. In fact, you can load one of these schematics and use the File Save As command to save it under another name. You can then edit this new schematic to customize it to your needs.

Elements placed in the ADSU4 RPM schematic include CY4 components and FMAPs. The CY4 symbol gives you the ability to specify fast carry logic functionality from the schematic. Fast carry logic is a hardware feature in XC4000E parts that allows very fast arithmetic-type functions.

The FMAPs map logic functions to function generators in Configurable Logic Blocks (CLBs), which are arranged in a rectangular grid in the die. Both CY4 symbols and FMAP symbols have RLOC attributes. RLOCs are attached to the symbols that assign relative locations to the CLBs. You can use carry symbols as well as FMAPs and other mapping components in your own schematics. However, knowledge of them is not necessary to use RPMs. Only expert users should create macros containing carry logic and FMAPs. For a description of these components, see the XACT Libraries Guide.

Push into the ADSU4 schematic as follows:

1. Press F2 key.
   
   
2. Select ADSU4.
   
   
3. Open the schematic underneath adsu4.
   
   
4. Use the F8 key (or stroke 159) to zoom into the upper portion of the schematic as shown in the following figure.
   
   

   Figure 9.38 Upper Portion of the ADSU4 RPM Schematic

5. Press F2 key to unselect everything.
   
   
6. Select the FMAP component in the upper right corner.
   
   
7. Select Report Object Selected All.
   
   A text window appears displaying the attributes on the symbol, as shown in the following figure. The RLOC attribute is set to R0C0.G, indicating that this function is mapped to the G function generator of the upper-left corner (row zero, column zero) CLB in the RPM. RPM origins are in the upper left-hand corner. (You can also call up a report with the 1474123 stroke, which looks like a lowercase “r”.)
   
   

   Figure 9.39 RLOC Attribute on FMAP Component

8. Close the text window to return to the adsu4 schematic window.
   
   
9. Use the scroll bars on the sides of the window or double-click the middle mouse button to pan around the schematic and look at the RLOCs.
   
   Note that logic is mapped to three CLBs, designated as R0C0, R1C0, and R2C0. Therefore, this RPM uses three CLBs that are arranged in a column. Information on the number of CLBs used and the shape of the logic block is available for each RPM in the XACT Libraries Guide. These locations are relative, not absolute. The macro is not defined as placed in the uppermost CLB in the left most column. Regardless of the RPM's absolute location, the logic associated with the FMAP with the location R0C0 is always at the top, R1C0 is in the CLB directly below, and so on.
   
   
10. Close the adsu4 schematic and return to the ALU schematic.
    
    

Opening the Calc Schematic

Close all open schematic or symbol windows except for the top-level Calc schematic window. If the Calc window is closed, open it. The Calc schematic appears on the screen.

Using the XC4000E Oscillator

If your design is not targeted for the XC4000E family, read this section, but do not perform any of the commands.

The XC4000E family devices contain an on-chip clock generator, which makes it unnecessary to use an external circuit for this purpose. The on-board clock circuitry is not precise, but is suitable for designs that do not need a highly accurate clock, such as the Calc design.

Figure 9.40 CLOCKGEN Schematic

The CLOCKGEN schematic contains an XC4000E library part, OSC4. This symbol represents the on-chip oscillator that generates nominal clock frequencies of 8 MHz, 500 KHz, 16 KHz, 490 Hz, and 15 Hz. The Calc design uses the 15-Hz output from this component when targeted for XC4000E family designs. The clock output from OSC4 is buffered through a BUFG global clock buffer.

XC4000E family devices have eight on-chip clock buffers, one BUFGP (primary global buffer) and one BUFGS (secondary global buffer) in each corner of the device. Although it is possible to use them for other purposes, BUFGPs are best used to route externally-generated clock signals. BUFGSs have more flexibility, and can be used to route any large fan-out net, even if it is internally sourced. A BUFG symbol can represent either type of buffer, and allows the implementation software to choose which type of global buffer is best in each situation. BUFG also facilitates design retargeting to other Xilinx device families, since it can represent any type of global buffer in any family. The BUFG in the Calc design is substituted for a BUFGS during design implementation, because the clock is generated internally by the on-chip oscillator. See the XACT Libraries Guide and the The Xilinx Programmable Logic Data Book for more information on global clock buffers for Xilinx devices.