FPGA Compiler reports area with the Report FPGA command as follows.
report_fpga
The statistics reported by this command include the number of the following elements used in your design.
The Report FPGA command also reports the number of CLBs used for the design on the basis of the mapping performed by FPGA compiler.
The Report FPGA command provides an accurate CLB count when FPGA Compiler provides packing information to the place and route tools. However, the Synopsys output netlist suppresses packing data. As a result, the actual CLB count can vary between FPGA Compiler's Report FPGA count and MAP's mapping report. The Synopsys output netlist suppresses packing data because it impacts the routability of the design. For better results with the Xilinx tools, ensure that the software controls the allocation of flip-flops and function generators to CLBs. You can reactivate the Synopsys packing data.
The reported number of CLBs can vary during design implementation, however, the number of flip-flops, F, G, and H function generators does not. Therefore, you can accurately assess a design's area in these terms. Use the Synopsys CLB count as a conservative estimate.
Run the Report FPGA command after compiling your design because the Compile command maps the logic into CLBs and IOBs. Also, run this command before replacing the CLB and IOBs with gates (before running the Replace FPGA command).
The area utilization report below illustrates the Report FPGA output for the bidi_reg design. The report shows the number of CLBs used.
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