The Synopsys tools report all delays in nanoseconds. The reported delays include logic-level and interconnect delays. Because FPGA Compiler synthesizes CLBs and IOBs (XC4000E/L/EX/XL/XLA/XV devices) or LUTs and flip-flops (XC3000A, XC3100A/L, and XC5200 devices), it reports logic-level delays with a higher degree of accuracy than Design Compiler. Because Design Compiler synthesizes only logic gates, it provides only estimates of logic-level delays. Logic-level delays are worst case.
Both FPGA Compiler and Design Compiler estimate possible interconnect delays on the basis of a net's fanout. These estimates allow you to evaluate your design's performance prior to performing place and route. FPGA Compiler applies the wire-load model only to nets between CLBs and IOBs (XC4000E/L/EX/XL/XLA/XV devices) or between LUTs, I/Os, and flip-flops (XC3000A, XC3100A/L, and XC5200 devices). Design Compiler's estimates of interconnect delays based on fanout match FPGA Compiler's. However, because Design Compiler does not have information on how your design maps and packs into LUTs or CLBs, it applies the wire-load model to every net in your design. This results in a less accurate net contribution to overall path delays. You can use either average or worst-case wire-load models.
To evaluate the timing results, use the Report Timing command.
report_timing
Refer to the Synopsys Design Compiler Family Reference Manual for information on other report options.
Run the Report Timing command after compiling the design because the Compile command maps the logic into CLBs and IOBs, and before running the Replace FPGA command, which replaces the CLBs and IOBs with gates.
Only XC4000E/L/EX/XL/XLA/XV designs require the Replace FPGA command.
Synopsys assigns a default “average case” wire-load model to all nets in your design. Refer to the “Setting the Wire-Load Model” section at the beginning of this chapter for more information.
