Once your design meets your timing and area requirements, you can save the design as a DB file. For XC4000E/L/EX/XL/XLA/XV devices and FPGA Compiler only, replace the CLBs and IOBs with gates. For FPGA Compiler, set the design part type and any other supporting information. Then, write and save your design as a netlist in either XNF (FPGA Compiler) or EDIF (Design Compiler) formats.
Save the Synopsys database file before converting your design to gates by running the Replace FPGA command (XC4000E/L/EX/XL/XLA/XV and FPGA Compiler only). If you use the Replace FPGA command options for debugging, such as Group TLUS and Group Cell, save the DB file before running these debugging options.
To save the DB file, choose one of the following methods.
Save AsThis section applies to XC4000E/L/EX/XL/XLA/XV devices and FPGA Compiler.
After compiling with FPGA Compiler, XC4000E/L/EX/XL/XLA/XV designs contain CLB and IOB elements used to determine the best implementation of a design for a given set of constraints. Before writing an output netlist, you must convert these CLBs and IOBs into gates recognizable by the Xilinx software. The mapping information passes to the netlist with the FMAP, HMAP, and, optionally, BLKNM parameters, so you can map your design according to FPGA Compiler's directions.
Enter the following command at the command line at the top level of your design.
replace_fpga
Running the Replace FPGA command with either the Group Cells or the Group TLUS option and then writing the netlist file generates netlists for each level of hierarchy in your design. If you use the Group Cells option, each CLB transforms into a level of hierarchy with a netlist created for each CLB. Similarly, if you use the Group TLUS option, each function generator transforms into a level of hierarchy.
If you use these options, perform the following steps.
This section applies only to FPGA Compiler.
By default, the FPGA Compiler XNF Writer contains information on how it should map the logic into the CLB and IOBs. FPGA Compiler uses the FMAP and HMAP symbols to map Boolean logic into F and H function generators, and the BLKNM attribute to group flip-flops and function generators into a CLB.
When the XNF Writer includes FPGA Compiler's mapping information in the netlist, the accuracy of the estimated timing information increases.
FPGA Compiler provides efficient mapping information, so leave the mapping on. However, using FPGA Compiler to perform mapping decreases the MAP program's processing time.
Block names can restrict placement and routing. For this reason, FPGA Compiler by default does not write the BLKNM attributes.
The following section describes how to remove FMAP and HMAP information and restore BLKNM attributes.
To remove the FMAP and HMAP mapping, enter the following at the command line.
set_attribute find(design,"*") \
"xnfout_write_map_symbols" -type boolean FALSE
To restore the creation of BLKNM attributes, enter the following at the command line.
set_attribute find(design,"*") \
"xnfout_use_blknames" -type boolean TRUE
Type the following command at the command line to select a specific part for the design. The following example uses a 4005EPC84-4 device.
set_attribute design_name "part" \
-type string "4005epc84-4"
You can also specify the part type when running NGDBuild.
Follow the instructions in the appropriate section below to save your design netlist file.
Save your design netlist file in EDIF format with a .sedif extension to denote its source. NGDBuild processes netlists from Synopsys in a slightly different way than other netlists. The .sedif extension indicates to NGDBuild to use the Synopsys design flow.
You can save your design as an SEDIF file by either of the following methods.
Save AsSave your design netlist file in XNF format with a .sxnf extension to denote its source. NGDBuild processes netlists from Synopsys in a slightly different way than other netlists. The .sxnf extension indicates to NGDBuild to use the Synopsys design flow.
The XNF netlist format can convey your design's logical hierarchy only with hierarchical instance names and net names. Therefore, flatten your design's hierarchy prior to writing out a netlist in XNF format. Although this removes the design hierarchy from the Synopsys design database, hierarchical net and instance names remain unchanged. As a result, the XNF file still conveys your design's hierarchy. After you have flattened your design, you can then write out the netlist.
You can save your design as an SXNF file by either of the following methods.
Command Window Save As