Performing Boundary Scans

The XC4000E/L/EX/XL/XLA/XV and XC5200 FPGA devices contain boundary-scan facilities compatible with IEEE Standard 1149.1. Refer to the Development System Reference Guide for a detailed description of the XC4000E/L/EX/XL/XLA/XV and XC5200 boundary scan capabilities.

Xilinx parts support external (I/O and interconnect) testing and have limited support for internal self-test.

Full access to the built-in boundary-scan logic exists between power-up and the start of configuration. Optionally, specify boundary scan in the design to access built-in logic after configuration. During configuration, you can use the Sample/Preload and Bypass instructions only.

To make boundary-scan logic active in a configured FPGA device, include the boundary-scan cell and its related I/O cells in the configuration data of your design. For HDL designs, you must instantiate the boundary-scan symbol, BSCAN, and the boundary scan I/O pins, TDI, TMS, TCK, and TDO.

WARNING

Do not use the following FPGA Compiler boundary scan commands because they do not work with FPGA devices.

set jtag implementation

set jtag instruction

set jtag port

The following figure illustrates the BSCAN symbol instantiated into an HDL design.

Figure 3.5 Boundary Scan Symbol Instantiation in XC4000 Family

The following examples show the code used to instantiate the cells in the previous figure. Additionally, the examples include code samples for the XC5200 family. The VHDL code for instantiating BSCAN in the XC5200 family follows.

NOTE

You must apply a Dont Touch attribute on all of the following instantiated components.

entity example is port (a, b: in bit; c: out bit); end example;

architecture xilinx of example is component bscan port(tdi, tms, tck: in bit; tdo: out bit); end component;

component tck port ( i : out bit ); end component;

component tdi port ( i : out bit ); end component;

component tms port ( i : out bit ); end component;

component tdo port ( o : in bit ); end component;

component ibuf port (i: in bit; o: out bit); end component;

component obuf port(i: in bit; o: out bit); end component;

signal tck_net, tck_net_in : bit; signal tdi_net, tdi_net_in : bit; signal tms_net, tms_net_in : bit; signal tdo_net, tdo_net_out : bit;

begin u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net, tdo=>tdo_net_out); u2: ibuf port map(i=>tck_net_in, o=>tck_net); u3: ibuf port map(i=>tdi_net_in, o=>tdi_net); u4: ibuf port map(i=>tms_net_in, o=>tms_net); u5: obuf port map(i=>tdo_net_out, o=>tdo_net); u6: tck port map (i=>tck_net_in); u7: tdi port map (i=>tdi_net_in); u8: tms port map (i=>tms_net_in); u9: tdo port map (o=>tdo_net);

process(b) begin if(b'event and b='1') then c <= a; end if; end process;

end xilinx;

The following shows the Verilog code for instantiating BSCAN in the XC5200 family.

module example (a,b,c); input a, b; output c;

reg c; wire tck_net, tck_net_in; wire tdi_net, tdi_net_in; wire tms_net, tms_net_in; wire tdo_net, tdo_net_out;

BSCAN u1 (.TDI(tdi_net), .TMS(tms_net), .TCK(tck_net), .TDO(tdo_net)); TDI u2 (.I(tdi_net_in)); TMS u3 (.I(tms_net_in)); TCK u4 (.I(tck_net_in)); TDO u5 (.O(tdo_net_out));

IBUF u6 (.I(tdi_net_in), .O(tdi_net)); IBUF u7 (.I(tms_net_in), .O(tms_net)); IBUF u8 (.I(tck_net_in), .O(tck_net));

OBUF u9 (.I(tdo_net), .O(tdo_net_out));

always@(posedge b) c<=a; endmodule

The Verilog code for instantiating BSCAN in XC4000/XC4000E appears in the following example. Note the use of upper and lower case in the sample.

module example (a,b,c); input a, b; output c; reg c; wire tck_net; wire tdi_net; wire tms_net; wire tdo_net; BSCAN u1 (.TDI(tdi_net), .TMS(tms_net), .TCK(tck_net), .TDO(tdo_net)); TDI u2 (.I(tdi_net)); TMS u3 (.I(tms_net)); TCK u4 (.I(tck_net)); TDO u5 (.O(tdo_net)); always@(posedge b) c<=a; endmodule

The VHDL code for instantiating BSCAN in XC4000/XC4000E example follows.