Previous

Using Memory

You can use on-chip RAM for status registers, index registers, counter storage, distributed shift registers, LIFO stacks, and FIFO buffers.

The XC4000 family can efficiently implement RAM and ROM using CLB function generators. Implement a ROM by describing it behaviorally as shown in the “Implementing XC4000E/L/EX/XL/XV ROMs” section. Alternatively, the XSI XC4000E/L/EX/XL/XV libraries contain 16 x 1 (16 deep x 1 wide) and 32 x 1 (32 deep x 1 wide) RAM and ROM primitives and 16 x 1 dual-port RAM you can instantiate.

You can also implement memory using the LogiBLOX program. LogiBLOX can create RAM and ROM between 1-32 bits wide and 2-256 bits deep. Using LogiBLOX to add RAM or ROM to your design provides an efficient implementation of your memory in addition to a simulation model for Register Transfer Level (RTL) simulation.

For VHDL and Verilog examples of instantiating RAM in your designs using LogiBLOX, refer to the “Using LogiBLOX” chapter. Also, refer to the LogiBLOX Reference/User Guide for more information on LogiBLOX.

Implementing XC4000E/L/EX/XL/XV RAMs

Implement RAMs in your HDL with the following methods.

Behaviorally describing RAMs in VHDL creates combinatorial loops during compiling.

Implementing XC4000E/L/EX/XL/XV ROMs

Implement ROM in your HDL with the following methods.

To instantiate the ROM16 x 1 and ROM32 x 1 primitives into your design, connect the input and output pins to the appropriate signals. Use the DC Shell Set Attribute command to define the ROM value.

set_attribute “instance_name” \
xnf_init “rom_value” -type string

For example, if you gave the 16 x 1 ROM an instance name of “U1” and a hex value of F5A3, you can use the DC Shell Set Attribute command to set the ROM value as follows.

set_attribute “U1” xnf_init “F5A3” -type string

Compile calculates ROM content values by considering the 16 x 1 or 32 x 1 ROM's 16 or 32 1-bit locations as bits in a 16 or 32 bit word. For example, for a 32 x 1 ROM, specify an 8-digit hexadecimal (hex) value in place of the 4-digit hex value. See the “Implementing ROMs” figure.

Refer to the Application Note “Using Select-RAM Memory in XC4000 Series FPGAs” for more information.

Figure 3.4 Implementing ROMs

The 16 x 4 ROM VHDL and 16 x 4 ROM Verilog HDL examples illustrate how to define a ROM in VHDL and Verilog HDL, respectively. FPGA Compiler creates ROMs from optimized random logic gates implemented using function generators.

The 16 x 4 ROM RTL VHDL example follows.

-----------------------------------------
-- RTL 16x4 ROM Example --
-- rom16x4_4k.vhd --
-----------------------------------------

entity rom16x4_4k is
port ( ADDR: in INTEGER range 0 to 15;
DATA: out BIT_VECTOR (3 downto 0));
end rom16x4_4k;

architecture RTL of rom16x4_4k is

subtype ROM_WORD is BIT_VECTOR (3 downto 0);
type ROM_TABLE is array (0 to 15) of ROM_WORD;
constant ROM: ROM_TABLE := ROM_TABLE'(
ROM_WORD'(“0000”),
ROM_WORD'(“0001”),
ROM_WORD'(“0010”),
ROM_WORD'(“0100”),
ROM_WORD'(“1000”),
ROM_WORD'(“1000”),
ROM_WORD'(“1100”),
ROM_WORD'(“1010”),
ROM_WORD'(“1001”),
ROM_WORD'(“1001”),
ROM_WORD'(“1010”),
ROM_WORD'(“1100”),
ROM_WORD'(“1001”),
ROM_WORD'(“1001”),
ROM_WORD'(“1101”),
ROM_WORD'(“1111”),
begin
DATA <= ROM(ADDR); -- Read from the ROM
end RTL;

The 16 x 4 ROM RTL Verilog example follows.

module rom16x4_4k(ADDR, DATA) ;
input [3:0] ADDR ;
output [3:0] DATA ;

reg [3:0] DATA ;

always @(ADDR)
begin
case (ADDR)
4'b0000 : DATA = 4'b0000 ;
4'b0001 : DATA = 4'b0001 ;
4'b0010 : DATA = 4'b0010 ;
4'b0011 : DATA = 4'b0100 ;
4'b0100 : DATA = 4'b1000 ;
4'b0101 : DATA = 4'b1000 ;
4'b0110 : DATA = 4'b1100 ;
4'b0111 : DATA = 4'b1010 ;
4'b1000 : DATA = 4'b1001 ;
4'b1001 : DATA = 4'b1001 ;
4'b1010 : DATA = 4'b1010 ;
4'b1011 : DATA = 4'b1100 ;
4'b1100 : DATA = 4'b1001 ;
4'b1101 : DATA = 4'b1001 ;
4'b1110 : DATA = 4'b1101 ;
4'b1111 : DATA = 4'b1111 ;
endcase
end

endmodule

Next