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Inserting Clock Buffers

For designs with global signals, use global clock buffers to take advantage of the low-skew, high-drive capabilities of the primary global clock buffer (BUFGP) and the secondary global clock buffer (BUFGS). When you use the Insert Pads command, FPGA Compiler automatically inserts a generic global clock buffer (BUFG) whenever an input signal drives a clock signal. The Xilinx implementation software automatically selects the clock buffer appropriate for your specified design constraints. If you want to use a specific global buffer, you must instantiate it.

You can instantiate an architecture-specific buffer if you understand the architecture and want to specify how to use the resources. Each XC4000E/L device contains four primary and four secondary global buffers that share the same routing resources. XC4000EX/XL/XLA/XV devices have sixteen global buffers; each buffer has its own routing resources. For all architectures, use the BUFG for up to four low-skew, high-fanout clock signals.

You can use BUFGS to buffer high-fanout, low-skew signals sourced from inside the FPGA. To access the secondary global clock buffer for an internal signal, instantiate the BUFGS_F cell.

Additionally, you can use BUFGP to distribute signals applied to the FPGA from an external source. A primary global buffer can globally distribute internal signals, however, the signals must drive an external pin.

Controlling Clock Buffer Insertion

Because FPGA Compiler assigns a BUFG to any input signal that drives a clock signal, your design can contain too many clock buffers. The following examples illustrate how to control clock buffer insertion.

The following two examples also illustrate a gated clock using VHDL and Verilog HDL, respectively. By default, Synopsys assigns the signals IN1, IN2, IN3, IN4, and CLK to a BUFG because they ultimately connect to a clock pin.

The gate_clock VHDL example follows.

entity gate_clock is
port (IN1, IN2, IN3, IN4, IN5, CLK, LOAD: in BIT;
OUT1: buffer BIT);
end gate_clock

architecture RTL of gate_clock is
signal GATECLK: BIT;
begin
GATECLK <= not((((IN1 and IN2) and IN3) and IN4) and CLK);
process (GATECLK)
begin
if (GATECLK' event and GATECLK= `1') then
if (LOAD= `1') then
OUT1 <= IN5;
else
OUT1 <= OUT1;
end if;
end if;
end process;
end RTL;

The gate_clock Verilog HDL example follows.

module gate_clock(IN1, IN2, IN3, IN4, IN5, CLK, LOAD, OUT1) ;
input IN1 ;
input IN2 ;
input IN3 ;
input IN4 ;
input IN5 ;
input CLK ;
input LOAD ;
output OUT1;

reg OUT1;

wire GATECLK ;

assign GATECLK = ~(IN1 & IN2 & IN3 & IN4 & CLK) ;

always @(posedge GATECLK)
begin
if (LOAD == 1'b1)
OUT1 = IN5 ;
end

endmodule

FPGA Compiler identifies clock ports by tracing back from the clock pins on the flip-flops. In the following figure, the inputs to the 5-input NAND gate all have a BUFG inserted.

Figure 3.3 Gated Clock After Pad Insertion

If your design contains gated clocks or has more than four input pins that drive clock pins, disable the input pins to stop insertion of a BUFG. Refer to the “Preventing the Insertion of Clock Buffers” section in this chapter.

Determining the Number of Clock Buffers

To determine how many clock buffers FPGA Compiler inserted in your design, use the Report FPGA command after using the Insert Pads or Compile command. Enter the Report FPGA command as follows.

report_fpga

The following example shows the output produced when running the Report FPGA command on the previous gated clock design.

Although clock pads are IOBs, this report lists them separately.

*************************************
Report : fpga
Design : gate_clock
Version: v3.4b
Date : Tues Dec 10 09:22:21 1996
*************************************

Xilinx FPGA Design Statistics
-----------------------------

FG Function Generators 1
H Function Generators 1
Number of CLB cells: 1
Number of Hard Macros and
Other Cells: 0
Number of CLBs in
Other Cells: 0
Total Number of CLBs: 1

Number of Ports: 8
Number of Clock Pads: 5
Number of IOBs: 3

Number of Flip Flops: 1
Number of 3-State Buffers: 0

Total Number of Cells: 9

Preventing the Insertion of Clock Buffers

To prevent FPGA Compiler from inserting the BUFG primitive, specify the Set Pad Type command with the following options before inserting the pads.

set_pad_type -no_clock {clock_ports}

Replace clock_ports with the name of the input pins where you do not want a clock buffer inserted. For the gated clock VHDL and Verilog examples, enter the following.

set_pad_type -no_clock {IN1, IN2, IN3, IN4, CLK}

Then follow the normal procedures to set the ports as pads and insert the pads as follows.

set_port_is_pad “*”

insert_pads

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