Configuring IOBs

This section describes how to configure FPGA IOBs. You must implement some features manually, but FPGA Compiler performs the following optimization functions automatically.

Inserts input buffers (IBUF) and output buffers (OBUF)
Inserts IBUFs and 3-state output buffers (OBUFT) for bidirectional I/O (IOBUF)
Inserts a clock buffer for ports driving clock pins (BUFG)

NOTE
The following functions apply only to FPGAs with I/O flip-flops.
Optimizes a flip-flop (IFD) without a clock enable, or latch (ILD_1) attached to input buffers into the IOB
Optimizes a flip-flop without a clock enable attached to output buffers into the IOB (OFD)

Indicate which ports in your design to use for chip-level I/Os with the Set Port Is Pad command. The Insert Pads command adds the correct buffers to the ports declared as pads, as shown in the following example.

set_port_is_pad “*” insert_pads

All Architectures

This section includes general information about IOBs that applies to all supported device architectures.

Optimizing Inputs

FPGA Compiler optimizes any flip-flops connected to an input port into the IOB if the flip-flop or latch does not use the Clock Enable, Direct Clear, or Preset pin.

You can configure the buffered input signal that drives the data input of a storage element as either a flip-flop or a latch. You can use the buffered signal in conjunction with the input flip-flop or latch.

A delay buffer added to the signal feeding the data input of the input flip-flop/latch avoids a possible hold time violation. Instantiating a flip-flop or latch, such as an IFD_F or ILD_1F, removes this delay because these cells include a NODELAY attribute. Refer to the “XSI Library Primitives” appendix for a complete list of primitives that include NODELAY attributes.

Optimizing Outputs

FPGA Compiler has the ability to optimize flip-flops attached to output pad in the IOB. However, FPGA Compiler cannot optimize flip-flops in an IOB configured as a bidirectional pad.

Understanding and Using Slew Rate

The output buffers have a default slow slew rate that alleviates ground-bounce problems and the option of a fast slew rate that reduces the output delay. The SLOW option increases the transition time and reduces the noise level. The FAST option decreases the transition time and increases the noise level.

WARNING

Synopsys and Xilinx define slew rate using opposite terms. Synopsys uses slew control, whereas Xilinx uses slew rate. For example, the Synopsys HIGH slew control is equivalent to the Xilinx SLOW slew rate.

The XSI libraries contain two types of output buffers. The default output buffer has a slow slew rate. An additional output buffer with a fast slew rate has a FAST attribute assigned to it, OBUF_F (output buffer) and OBUFT_F (3-state output buffer), also in the XSI libraries. To avoid possible ground-bounce problems, use the default SLOW as the slew rate. Assign a FAST slew rate only to output buffers that require additional speed.

NOTE

FPGA Compiler V3.3 and later versions use a default slew rate of slow.

To change any output port to a FAST slew rate, use the following command. Replace port with the name of the output port.

set_pad_type -slewrate NONE {port}

Set this command before implementing the Insert Pads commands.

Table 3_1 XC4000E/EX/XV Slew Rate Settings

Xilinx Slew Rate	Synopsys Slew Control Attribute	FPGA Compiler Command
SLOW	HIGH	`set_pad_type` `-slewrate HIGH` `{`port`}`
FAST	NONE	`set_pad_type` `-slewrate NONE {`port`}`

XC3000A/L and XC3100A/L IOBs

This section describes XC3000A/L and XC3100A/L IOBs.

Using Input Blocks

Select input thresholds globally with TTL/CMOS. Internal pull-up resistors can optionally attach to the I/O pad. You can make inputs registered or latched. You can select register and latch setup time.

In the default configuration, the input register or latch has positive setup and negative hold time (when used in conjunction with a global clock network). Reducing input setup time produces a small positive hold time.

Registered and latched inputs become available simultaneously with direct input. You have no clock or latch-enable or asynchronous set/reset control on input registers and latches, but you can control the initial state of input registers and latches.

Using Output Blocks

You can select the output driver slew rate. The output driver by default uses a slow slew rate setting to reduce system noise and power. A faster slew rate decreases chip-to-out propagation delay.

You can make outputs tristate and you can register them.

You cannot apply clock-enable or asynchronous set/reset control on output registers but you can control the initial state of output registers.

Using Bidirectional Mode

You cannot use internal pull-up resistors in this mode.

You can select the output driver slew rate. The output driver by default uses a slow slew rate setting to reduce system noise and power. A faster slew rate decreases chip-to-out propagation delay.

Select input thresholds globally with TTL/CMOS. Input can be registered or latched and you can select register and latch setup time.

You cannot apply clock or latch-enable or asynchronous set/reset control on input registers and latches. Direct input enables simultaneous availability of registered and latched input.

You can control the initial state of input registers and latches, and you can register output.

You cannot apply clock-enable or asynchronous set/reset control on output registers, but you can control the initial state of output registers.

XC4000E/L/EX/XL/XLA/XV IOBs

This section describes XC4000E/L/EX/XL/XLA/XV IOBs.

Using Input Blocks

Select input thresholds globally with TTL/CMOS. Specify an internal pull-up/pull-down resistor that can optionally attach to an I/O pad.

You can make inputs registered or latched and you can select register and latch setup time.

In the default configuration, the input register or latch has positive setup and zero hold time (when used in conjunction with a global clock network). For XC4000 devices, reducing input setup time slightly increases hold time. For XC4000EX/XL/XLA/XV devices, three setup and hold delay adjustments allow setup versus hold parameter tuning.

Direct input enables simultaneous availability of registered and latched input. You cannot apply asynchronous set/reset control on input registers and latches, but you can apply clocks and latches on input register and latches.

FPGA Compiler cannot infer I/O registers and latches with clock and latch-enables.

You can control the initial state of input registers and latches.

Using Output Blocks

You can select the output driver slew rate. By default the output driver uses a slow slew rate setting to reduce system noise and power. A faster slew rate decreases chip-to-out propagation delay

You can register outputs and make them tristate. You cannot enable asynchronous set/reset control on output registers, but you can specify clock-enable on output registers. FPGA Compiler cannot infer I/O registers and latches with clock and latch enables.

You can control the initial state of output registers.

Perform 2-to-1 multiplexing or 2-input function directly in the output path of an IOB (XC4000EX/XL/XV only). You can trade an output register for a 2-input function or multiplexer. Additionally, you must instantiate the following primitives (valid for XC4000EX/XL/XLA/XV/XLT). See the “XSI Library Primitives” appendix for more details.

OAND2
OMUX2
ONAND2
ONOR2
OOR2
OXNOR2
OXOR2

FPGA Compiler cannot infer output drivers containing a 2-input function or output multiplexer.

Using Bidirectional Mode

You can select the output driver slew rate. By default the output driver uses a slow slew rate setting to reduce system noise and power. Faster slew rates decrease chip-to-out propagation delay.

Select input thresholds globally with TTL/CMOS. Input can be registered or latched and you can select register and latch setup time.

In the default configuration, the input register or latch has positive setup and negative hold time (when used in conjunction with a global clock network). This corresponds to a full delay. Reducing input setup time slightly increases hold time.

You cannot enable asynchronous set/reset control on input registers and latches. Direct input makes registered and latched input available simultaneously.

You can specify clock and latch-enable on input registers and latches. FPGA Compiler cannot infer I/O registers or latches with clock or latch enables.

You can control initial states of I/O registers and latches. You can register output.

You cannot enable asynchronous set/reset control on output registers, but you can specify clock-enable on output registers. FPGA Compiler cannot infer I/O registers and latches with clock or latch enables.

You can control the initial state of output registers.

Perform 2-to-1 multiplexing or 2-input function directly in the output path of an IOB. You can trade an output register for a 2-input function or multiplexer. FPGA Compiler cannot infer output drivers containing 2-input functions or output multiplexers. Additionally, you must instantiate the OMUX2, ONADN2, ONOR2, and OOR2 primitives. See the “XSI Library Primitives” appendix for more details.

Using XC5200 IOBs

This section describes XC5200 IOBs.

Using Input Blocks

Select input thresholds globally with TTL/CMOS. Specify an internal pull-up/pull-down resistor that can optionally attach to an I/O pad.

IOBs can contain no input registers, although you can emulate this functionality using the latch/flip-flop in the adjacent CLB. Additionally, CLB registers and latches have clock or latch-enables and asynchronous reset inputs.

The IOB input path has an optional delay with which you can adjust input setup and hold times. By default an input register or latch has a positive setup and negative hold time (when used in conjunction with a global clock network). Reducing input setup time slightly increases hold time.

Using Output Blocks

You can select the output driver slew rate. By default the output driver uses a slow slew rate setting to reduce system noise and power. A faster slew rate decreases chip-to-out propagation delay.

You can make outputs tristate.

IOBs contain no output registers, although you can emulate this functionality using the latch or flip-flop in the adjacent CLB. Additionally, CLB registers and latches have clock or latch-enables and asynchronous reset inputs.

Using Bidirectional Mode

Select input thresholds globally with TTL/CMOS. Have an internal pull-up/pull-down resistor that can optionally attach to an I/O pad.

IOBs contain no input registers, although you can emulate this functionality using the latch/flip-flop in the adjacent CLB. Additionally, CLB registers and latches have clock or latch-enables and asynchronous reset inputs.

The IOB input path has an optional delay with which you can adjust input setup and hold times. By default the input register or latch has a positive setup and negative hold time (when used in conjunction with a global clock network). Reducing input setup time slightly increases hold time.

You can select the output driver slew rate. By default the output driver uses a slow slew rate setting to reduce system noise and power. A faster slew rate decreases chip-to-out propagation delay.

You can make outputs tristate.

Assigning and Prohibiting Pad Locations

You can specify pad locations in your synthesis script or in a Xilinx User Constraints File (UCF). To assign pad locations in your synthesis DC script, include the following command in your script, replacing pad and pin number with the appropriate values.

set_attribute pad“pad_location” \ -type string “pin number”

Refer to The Programmable Logic Data Book, available on the Xilinx Web site at (http://www.xilinx.com), for the locations and name of the pins. For more information on the UCF, refer to the Development System Reference Guide or the Libraries Guide.

Implementing 3-State Registered Output

FPGA Compiler infers the use of 3-state output flip-flops, such as OFDT, under the following two conditions.

The flip-flop must directly drive the 3-state signal.
The HDL code of the flip-flop must reside in the same process as the 3-state HDL code.

The following sections illustrate a flip-flop that does not directly drive the 3-state signal and one that does directly drive the 3-state signal.

Example of Not Directly Driving the 3-State Signal

If any logic exists between the flip-flop and the 3-state signal connected to the output flip-flop, FPGA Compiler does not infer a 3-state output flip-flop. The following VHDL and Verilog examples illustrate a flip-flop not directly driving a 3-state output flip-flop. The “No Output Register Inferred” figure shows a schematic representation.

The three_ex1 VHDL example follows.

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity three_ex1 is port (BUS_IN, EN, CLK: in STD_LOGIC; BUS_OUT: out STD_LOGIC); end three_ex1; architecture RTL of three_ex1 is signal BUS_IN_REG, BUS_OUT_REG: STD_LOGIC; begin sync: process (CLK) begin if (CLK' event and CLK= `1') then BUS_IN_REG <= BUS_IN; BUS_OUT_REG <= BUS_IN_REG; end if; end process; BUS_OUT <= BUS_OUT_REG when (EN= `0') else `Z'; end RTL;

The three_ex1 Verilog example follows.

module three_ex1(BUS_IN, EN, CLK, BUS_OUT); input BUS_IN ; input EN ; input CLK ; output BUS_OUT ; reg BUS_OUT_REG, BUS_IN_REG, BUS_OUT; always @(posedge CLK) begin BUS_OUT_REG = BUS_IN_REG ; BUS_IN_REG = BUS_IN ; end always @(EN or BUS_OUT_REG) begin if (!EN) BUS_OUT = BUS_OUT_REG; else BUS_OUT = 1'bz; end endmodule

Figure 3.1 No Output Register Inferred

Example of Directly Driving the 3-State Signal

The HDL code for the flip-flop must reside in the same process as the 3-state HDL code and must directly drive the 3-state output, as shown in the “sync” process in the following VHDL and Verilog examples. If the code meets these two conditions, FPGA Compiler infers a registered 3-state output, as illustrated by the “Output Register Inferred” figure.

Having the flip-flop and the 3-state signal in separate processes causes the insertion of additional logic between the flip-flop and the 3-state signal.

The three_ex2 VHDL example follows.

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity three_ex2 is port (BUS_IN, EN, CLK: in STD_LOGIC; BUS_OUT: out STD_LOGIC); end three_ex2; architecture RTL of three_ex2 is signal BUS_IN_REG: STD_LOGIC; begin sync: process (CLK, EN) begin if (CLK' event and CLK= `1') then BUS_IN_REG <= BUS_IN; if (EN= `0') then BUS_OUT <= BUS_IN_REG; else BUS_OUT <= `Z'; end if; end if; end process; end RTL;

The three_ex2 Verilog example follows.

module three_ex2(BUS_IN, EN, CLK, BUS_OUT) ; input BUS_IN ; input EN ; input CLK ; output BUS_OUT ; reg BUS_OUT ; reg BUS_IN_Q, BUS_IN_REG ; always @(posedge CLK) begin BUS_IN_Q = BUS_IN ; BUS_IN_REG = BUS_IN_Q ; if (!EN) BUS_OUT = BUS_IN_REG; else BUS_OUT = 1'bz; end endmodule

Figure 3.2 Output Register Inferred

Inserting Bidirectional I/Os

FPGA Compiler has the ability to insert non-registered bidirectional ports. Describe the 3-state signal that drives the output buffer in the same hierarchy level as the input signal, as in the bidi_reg.vhd and bidi_reg.v examples in the following section.

Instantiating a Registered Bidirectional I/O

The top-level design examples bidi_reg.vhd and bidi_reg.v instantiate a core design, reg4. In these examples, two clock buffers, CLOCK1 and CLOCK2, automatically infer a BUFG buffer. The reset and load signals, RST and LOADA, automatically infer an IBUF when you run the Set Port Is Pad and Insert Pads commands. However, FPGA Compiler cannot automatically infer the OFDT_F (3-state registered output buffers with a FAST slew rate) cells in bidirectional I/Os. Therefore, these cells and the IBUF instantiate into the top-level design.

The bidi_reg.vhd VHDL example follows.

library IEEE; use IEEE.std_logic_1164.all; entity bidi_reg is port (SIGA: input STD_LOGIC_VECTOR (3 downto 0); LOADA, CLOCK1, CLOCK2, RST: in STD_LOGIC); end bidi_reg; architecture STRUCTURE of bidi_reg is component reg4 port (INX: in STD_LOGIC_VECTOR (3 downto 0); LOAD, CLOCK, RESET: in STD_LOGIC; OUTX: buffer STD_LOGIC_VECTOR (3 downto 0)); end component; component OFDT_F port (D: in STD_LOGIC; C: in STD_LOGIC; T: in STD_LOGIC; O: out STD_LOGIC); end component; component IBUF port (I: in STD_LOGIC; O: out STD_LOGIC); end component; signal INA, OUTA: STD_LOGIC_VECTOR (3 downto 0); begin U5: reg4 port map (INA, LOADA, CLOCK1, RST, OUTA); U0: OFDT_F port map (OUTA(0), CLOCK2, LOADA, SIGA(0)); U1: OFDT_F port map (OUTA(1), CLOCK2, LOADA, SIGA(1)); U2: OFDT_F port map (OUTA(2), CLOCK2, LOADA, SIGA(2)); U3: OFDT_F port map (OUTA(3), CLOCK2, LOADA, SIGA(3)); U4: IBUF port map (SIGA(0), INA(0)); U6: IBUF port map (SIGA(1), INA(1)); U7: IBUF port map (SIGA(2), INA(2)); U8: IBUF port map (SIGA(3), INA(3)); end STRUCTURE;

The bidi_reg.v Verilog example follows.

module bidi_reg (SIGA, LOADA, CLOCK1, CLOCK2, RST) ; inout [3:0] SIGA ; input LOADA ; input CLOCK1 ; input CLOCK2 ; input RST ; wire [3:0] INA, OUTA ; // Netlist reg4 U5 (.INPUT(INA), .LD(LOADA), .CLOCK(CLOCK1), .RESET(RST), \ .OUT(OUTA)) ; OFDT_F U0 (.D(OUTA[0]), .C(CLOCK2), .T(LOADA), .O(SIGA[0])) ; OFDT_F U1 (.D(OUTA[1]), .C(CLOCK2), .T(LOADA), .O(SIGA[1])) ; OFDT_F U2 (.D(OUTA[2]), .C(CLOCK2), .T(LOADA), .O(SIGA[2])) ; OFDT_F U3 (.D(OUTA[3]), .C(CLOCK2), .T(LOADA), .O(SIGA[3])) ; IBUF U4 (.I(SIGA[0]), .O(INA[0])) ; IBUF U6 (.I(SIGA[1]), .O(INA[1])) ; IBUF U7 (.I(SIGA[2]), .O(INA[2])) ; IBUF U8 (.I(SIGA[3]), .O(INA[3])) ; endmodule

The backslash (“\”) character shows a line break required for formatting purposes.

Compiling Bidirectional I/O

Do not use the Set Port Is Pad command for the instantiated I/O cells. For example, in the bidi_reg.vhd example, use the following commands to insert the I/Os for the LOADA, RST, CLOCK1, and CLOCK2 signals only.

set_port_is_pad {LOADA RST CLOCK1 CLOCK2}

insert_pads

Before compiling the design, you must place a Dont Touch attribute on any instantiated I/O cells to prevent their alteration, as shown in the following example.

dont_touch {U0 U1 U2 U3 U6 U7 U8}

The following example shows the script files used to compile bidi_reg.vhd and bidi_reg.v.

The script file for bidi_reg.vhd example follows.

/* =============================================== */ /* Sample Script for Synopsys to Xilinx Using */ /* the FPGA Compiler */ /* Bidirectional Register Example. */ /* ================================================ */ /* +++++++++++++++++++++++++++++++++++++++++++++++ */ /* Read in the design */ /* +++++++++++++++++++++++++++++++++++++++++++++++ */ /* Set the top-level modules name for the design */ TOP = bidi_reg SUB = reg4 /* Set the Designer and Company name for documentation */ designer = “XSI Team” company = “Xilinx, Inc” /* Analyze and Elaborate the design file and specify the design file */ /* format */ analyze -format vhdl SUB + “.vhd” analyze -format vhdl TOP + “.vhd” elaborate TOP /* Set the current design to the top level */ current_design TOP /* Add pads to the design. Make sure the current design is the */ /* top-level module */ set_port_is_pad {LOADA RST CLOCK1 CLOCK2} insert_pads dont_touch {U0 U1 U2 U3 U4 U6 U7 U8} /* +++++++++++++++++++++++++++++++++++++++++++++++ */ /* Compile the design */ /* +++++++++++++++++++++++++++++++++++++++++++++++ */ /* Set the synthesis design constraints. */ remove_constraint -all /* Synthesize and optimize the design */ compile -map_effort med /* +++++++++++++++++++++++++++++++++++++++++++++++ */ /* Save the design */ /* +++++++++++++++++++++++++++++++++++++++++++++++ */ /* Write the design report file */ report_fpga > TOP + “.fpga” report_timing > TOP + “.timing” /* Write out the design to a DB file */ write -format db -hierarchy -output TOP + “.db” /* Replace CLBs and IOBs with gates */ replace_fpga /* Set the part type */ set_attribute TOP “part” -type string “4013epq208-3” /* Save design in XNF format as <design>.sxnf */ write -format xnf -hierarchy -output TOP + “.sxnf” /* Exit the Compiler. */ exit

The script file for bidi_reg.v example follows.

/* ================================================ */ /* Sample Script for Synopsys to Xilinx Using */ /* the FPGA Compiler */ /* Bidirectional Register Example. */ /* ================================================ */ /* ++++++++++++++++++++++++++++++++++++++++++++++++ */ /* Read in the design */ /* +++++++++++++++++++++++++++++++++++++++++++++ */ /* Set the top-level modules name for the design */ TOP = bidi_reg SUB = reg4 /* Set the Designer and Company name for documentation. */ designer = “XSI Team” company = “Xilinx, Inc” /* Analyze and Elaborate the design file and specify the */ /* design file format */ analyze -format verilog SUB + “.v” analyze -format verilog TOP + “.v” elaborate TOP /* Set the current design to the top level */ current_design TOP /* Add pads to the design. Make sure the current design is the */ /* top-level module. */ set_port_is_pad {LOADA RST CLOCK1 CLOCK2} insert_pads dont_touch {U0 U1 U2 U3 U4 U6 U7 U8} /* +++++++++++++++++++++++++++++++++++++++++++++++ */ /* Compile the design */ /* +++++++++++++++++++++++++++++++++++++++++++++++ */ /* Set the synthesis design constraints. */ remove_constraint -all /* Synthesize and optimize the design */ compile -map_effort med /* +++++++++++++++++++++++++++++++++++++++++++++++ */ /* Save the design */ /* +++++++++++++++++++++++++++++++++++++++++++++++ */ /* Write the design report file */ report_fpga > TOP + “.fpga” report_timing > TOP + “.timing” /* Write out the design to a DB file write -format db -hierarchy -output TOP + “.db” /* Replace CLBs and IOBs with gates */ replace_fpga /* Set the part type */ set_attribute TOP “part” -type string “4013epq208-3” /* Save design in XNF format as <design>.sxnf */ write -format xnf -hierarchy -output TOP + “.sxnf” /* Exit the Compiler. */ exit

Using Unbonded IOBs

In some package and device pairs, not all pads bond to a package pin. You can use these unbonded IOBs and the flip-flops inside them in your design by instantiating them in the HDL code. However, Synopsys cannot infer unbonded primitives.

A “_U” suffix indicates unbounded primitives. Refer to the “XSI Library Primitives” appendix for a complete listing of all unbonded cells.

Adding Pull-Up and Pull-Down Resistors

You can apply pull-up and pull-down resistors to chip-level I/O ports and you can use them internally. Use the following command to attach pull-up or pull-down resistors to I/O ports before you issue the Insert Pads command.

set_pad_type {-pullup | -pulldown} port_name

You can only instantiate internal pull-up and pull-down resistors. The following table shows which devices require pull-up/pull-down resistors.

Table 3_2 Instantiating Pull-up/Pull-down Resistors

XC3000A/L	XC4000E/L	XC4000EX/XL/XLA/XV	XC5200
Pull-up	Pull-up/ Pull-down	Pull-up/ Pull-down	Pull-up/ Pull-down

Refer to the “XSI Library Primitives” appendix for a listing of all cells and their pin names for instantiation.

See the “Configuring IOBs” section in this chapter for more information on pull-up and pull-down resistors for a specific device family.

Removing the Default Input Delay

The input flip-flops and latches have a default delay preceding the data to the input flip-flop or latch. This delay prevents any possible hold-time violations if you have a clock signal that also comes into the device and clocks the input flip-flop or latch.

You can remove this delay by instantiating a cell that includes the NODELAY attribute if you need additional input speed and have no possibility of a hold-time violation. The “XSI Library Primitives” appendix lists all cells that include a NODELAY attribute. Input flip-flops or latches with an “_F” suffix have a NODELAY attribute assigned to the cell.

Initializing the IOB Flip-Flop to Preset

You can initialize IOB flip-flops to either Clear or Preset in XC3000A/L and XC4000E/L/EX/XL/XV FPGAs. The default is Clear. To initialize an I/O flip-flop or latch to Preset, use the following command to attach an INIT=S attribute to the flip-flop.

set_attribute “register_name” xnf_init \ “S” type string

Replace register_name with the name of the I/O flip-flop.

You can instantiate I/O cells with the INIT=S attribute already assigned to them. Refer to the “XSI Library Primitives” appendix for a list of all cells and their pin names for instantiation.