Using LogiBLOX in the HDL Design Flow

You can instantiate LogiBLOX components in your HDL code to take advantage of their high-level functionality.

Express each LogiBLOX module in HDL code with a component declaration describing the module type and a component instantiation describing how the module connects to the other design elements.

Follow these steps to use the LogiBLOX program.

1. Invoke the Module Selector from an icon or from the command line.
   
   
2. Configure your project directory using the LogiBLOX Setup window. The default directory is your current directory.
   
   
3. Select a base module type (for example, Counter, Memory, or Shift-register)
   
   
4. Customize the module by selecting pins and specifying attributes.
   
   
5. Press the OK button after completely specifying a module. Pressing OK initiates the generation of a component instantiation declaration, an RTL model, and an implementation netlist.
   
   
6. Deposit the HDL module declaration or instantiation into your HDL design.
   
   
7. Complete the signal connections of the instantiated LogiBLOX module to the rest of your HDL design.
   
   
8. Conduct functional simulation on your design. The HDL simulator reads the component declaration and looks for an RTL model.
   
   
9. Apply a Dont Touch attribute to all LogiBLOX modules.
   
   
10. Implement your design by invoking the Xilinx implementation tools.
    
    
11. Simulate your post-layout design by converting your design back to a timing netlist and invoking the back-annotation flow.