Instantiating RAM
You can implement memory using LogiBLOX, creating RAM and ROM between 1 to 32 bits wide and 2 to 256 bits deep. Using LogiBLOX to add RAM or ROM to your design provides an efficient implementation of your memory in addition to a simulation model for RTL simulation.
NOTEFor Verilog designs, use the Remove Design command on instantiated LogiBLOX memory before writing out the design.
| You can instantiate RAM in your designs using LogiBLOX, as shown in the following VHDL and Verilog examples. A sample script file follows each example. Refer to the LogiBLOX Reference/User Guide for more information about using LogiBLOX.
The following example shows how to instantiate RAM using LogiBLOX with VHDL.
library IEEE;
use IEEE.std_logic_1164.all;
entity test is
port (ADDRESS: IN std_logic_vector(5 downto 0);
DATAOUT: OUT std_logic_vector(3 downto 0);
DATAIN: IN std_logic_vector(3 downto 0);
WRITEN: IN std_logic;
CLK: IN std_logic);
end test;
architecture inside of test is
component testram
port (A: IN std_logic_vector(5 downto 0);
DO: OUT std_logic_vector(3 downto 0);
DI: IN std_logic_vector(3 downto 0);
WR_EN: IN std_logic;
WR_CLK: IN std_logic);
end component;
begin
U0: testram port map(A=>ADDRESS,DO=>DATAOUT,DI=>DATAIN,
WR_EN=>WRITEN,WR_CLK=>CLK);
end inside;
/*=================================================*/
/* Sample Script for Synopsys to Xilinx Using */
/* FPGA Compiler with LogiBLOX Memory */
/* Targets the Xilinx XC4028EX-3 and assumes a */
/* VHDL source file by way of an example. */
/* */
/* For general use with XC4000E/EX architectures.*/
/* Not suitable for use with XC3000A/XC5200 */
/* architectures. */
/*=================================================*/
/* =============================================== */
/* Set the name of the design's top-level module. */
/* (Makes the script more readable and portable.) */
/* Also set some useful variables to record the */
/* designer and company name. */
/* =============================================== */
TOP = test
/* ========================== */
/* Note: Assumes design file- */
/* name and entity name are */
/* the same (minus extension) */
/* ========================== */
designer = "XSI Team"
company = "Xilinx, Inc"
part = "4028expg299-3"
/* ================================================= */
/* Analyze and Elaborate the design file and specify */
/* the design file format. */
/* ================================================= */
analyze -f vhdl TOP + ".vhd"
elaborate TOP
/* ================================================= */
/* Set the current design to the top level. */
/* ================================================= */
current_design TOP
/* ================================================= */
/* Set the synthesis design constraints. */
/* ================================================= */
remove_constraint -all
/* Some example constraints */
/* create_clock <clock_port_name> -period 50
set_input_delay 5 -clock <clock_port_name> \
{ <a_list_of_input_ports> }
set_output_delay 5 -clock <clock_port_name> \
{ <a_list_of_output_ports> }
set_max_delay 100 -from <source> -to <destination>
set_false_path -from <source> -to <destination> */
/* Place dont_touch on LogiBLOX instantiation */
set_dont_touch {U0}
/* ================================================= */
/* Indicate those ports on the top-level module that */
/* should become chip-level I/O pads. Assign any I/O */
/* attributes or parameters and perform the I/O */
/* synthesis. */
/* ================================================= */
set_port_is_pad "*"
/* Some example I/O parameters */
/* set_pad_type -pullup <port_name>
set_pad_type -no_clock all_inputs()
set_pad_type -clock <clock_port_name>
set_pad_type -exact BUFGS_F <hi_fanout_port_name>
set_pad_type -slewrate HIGH all_outputs() */
/* ============================= */
/* Note: Synopsys slew-control= */
/* HIGH is the same as Xilinx's */
/* slewrate=SLOW. Synopsys slew- */
/* control=LOW is same as Xilinx */
/* slewrate=FAST. */
/* ============================= */
insert_pads
/* ================================================= */
/* Synthesize and optimize the design */
/* =========
The following example shows how to instantiate RAM using LogiBLOX with Verilog.
module test(address,dataout,datain,writen,clk);
input [5:0] address;
output [3:0] dataout;
input [3:0] datain;
input writen;
input clk;
testram U0
( .A(address),
.DO(dataout),
.DI(datain),
.WR_EN(writen),
.WR_CLK(clk));
endmodule
//---------------------------------------------------
// LogiBLOX SYNC_RAM Module "testram"
// Created by LogiBLOX version M1.2.11
// on Sun May 18 19:34:35 1997
// Attributes
// MODTYPE = SYNC_RAM
// BUS_WIDTH = 4
// DEPTH = 64
//---------------------------------------------------
module testram(A, DO, DI, WR_EN, WR_CLK);
input [5:0] A;
output [3:0] DO;
input [3:0] DI;
input WR_EN;
input WR_CLK;
endmodule
/* ==================================================*/
/* Sample Script for Synopsys to Xilinx Using */
/* FPGA Compiler with */
/* LogiBLOX Memory */
/* */
/* Targets the Xilinx XC4028EX-3 and assumes a */
/* Verilog source file by way of an example. */
/* */
/* For general use with XC4000E/EX architectures. */
/* Not suitable for use with XC3000A/XC5200 */
/* architectures. */
/* ==================================================*/
/* ================================================= */
/* Set the name of the design's top-level module. */
/* (Makes the script more readable and portable.) */
/* Also set some useful variables to record the */
/* designer and company name. */
/* ================================================= */
TOP = test
/* ========================== */
/* Note: Assumes design file- */
/* name and entity name are */
/* the same (minus extension) */
/* ========================== */
designer = "XSI Team"
company = "Xilinx, Inc"
part = "4028expg299-3"
/* ================================================= */
/* Analyze and Elaborate the design file and specify */
/* the design file format. */
/* ================================================= */
read -f verilog "testram.v"
read -f verilog TOP + ".v"
/* ================================================= */
/* Set the current design to the top level. */
/* ================================================= */
current_design TOP
/* ================================================= */
/* Set the synthesis design constraints. */
/* ================================================= */
remove_constraint -all
/* Some example constraints */
/* create_clock <clock_port_name> -period 50
set_input_delay 5 -clock <clock_port_name> \
{ <a_list_of_input_ports> }
set_output_delay 5 -clock <clock_port_name> \
{ <a_list_of_output_ports> }
set_max_delay 100 -from <source> -to <destination>
set_false_path -from <source> -to <destination>
*/
/* Place dont_touch on LogiBLOX instantiation */
set_dont_touch {U0}
/* ================================================= */
/* Indicate those ports on the top-level module that */
/* should become chip-level I/O pads. Assign any I/O */
/* attributes or parameters and perform the I/O */
/* synthesis. */
/* ================================================= */
set_port_is_pad "*"
/* Some example I/O parameters */
/* set_pad_type -pullup <port_name>
set_pad_type -no_clock all_inputs()
set_pad_type -clock <clock_port_name>
set_pad_type -exact BUFGS_F <hi_fanout_port_name>
set_pad_type -slewrate HIGH all_outputs() */
/* ============================= */
/* Note: Synopsys slew-control= */
/* HIGH is the same as Xilinx's */
/* slewrate=SLOW. Synopsys slew- */
/* control=LOW is same as Xilinx */
/* slewrate=FAST. */
Instantiating RAM or ROM with FPGA Compiler
Use the following procedures and examples to instantiate a LogiBLOX RAM or ROM in Verilog or VHDL with FPGA Compiler.
- Create a LogiBLOX RAM/ROM with the LogiBLOX GUI.
When specifying options for LogiBLOX, specify the vendor type as Synopsys. Also specify in the LogiBLOX GUI whether you need Verilog or VHDL files.
- For Verilog, create an NGO, VEI, and V file. For VHDL, create a NGO, VHI, and VHD file.
The V and VHD files are simulation models. The VEI and VHI files are templates which assist in instantiating the LogiBLOX into your HDL. The NGO file is the actual LogiBLOX module for your design.
- For the Verilog flow, use the name of the NGO file as the name of the module instantiation in the Verilog code.
The VEI file contains the module name, pin names, and port names needed to instantiate the LogiBLOX memory. Do not just rename the VEI file to a V file. Use the VEI file as a template for instantiating the LogiBLOX memory in your design.
- For the Verilog flow, make an empty Verilog file for the LogiBLOX module to tell the Synopsys netlist writer the pin directions for the LogiBLOX module.
- A module with pin names and pin directions exists in the .vei file produced by LogiBLOX. Cut this empty module out and place it in a Verilog file with the same name as the LogiBLOX module you created.
Read this file into Synopsys during the compile of your design.
- For the Verilog flow, after instantiating the LogiBLOX into your design, place a Dont Touch attribute on every instantiated LogiBLOX instance.
- For the Verilog flow, Synthesize the design with the normal A1.5 XSI run script.
NOTEBefore writing out the netlist file, remove the LogiBLOX memory from the Synopsys memory. This prevents Synopsys from overwriting the LogiBLOX module.
|
- For VHDL, use the name of the NGO file as the name of the component instantiation in the VHDL code. The VHI file contains an example of how to instantiate the LogiBLOX into VHDL.
- For VHDL, after instantiating the LogiBLOX into your VHDL code, place a Dont Touch attribute on every instantiated LogiBLOX instance.
- For VHDL, synthesize the design. The synthesis run script for VHDL is the same as the standard A1.5 XSI run script.
The following example shows the testram LogiBLOX module V file created from the VEI file.
module testram(A, DO, DI, WR_EN, WR_CLK);
input [5:0] A;
output [3:0] DO;
input [3:0] DI;
input WR_EN;
input WR_CLK;
endmodule
The following example shows the instantiation of a LogiBLOX design in Verilog code.
module test(address,dataout,datain,writen,clk);
input [5:0] address;
output [3:0] dataout;
input [3:0] datain;
input writen;
input clk;
testram U0
( .A(address)
.DO(dataout),
.DI(datain),
.WR_EN(writen),
.WR_CLK(clk));
endmodule
The following example shows the run script for compiling a LogiBLOX design in Verilog.
read -f verilog “testram.v” read -f verilog “test.v”
set_port_is_pad “*” insert_pads
compile
replace_fpga
ungroup -all -flatten
write_script test.dc
sh dc2ncf test.dc
remove_design testram
write -f xnf -h -o “test.sxnf”
The following example shows an instantiation of a LogiBLOX design in VHDL code.
library IEEE;
use IEEE.std_logic_1164.all;
entity test is
port (ADDRESS: IN std_logic_vector(5 downto 0);
DATAOUT: OUT std_logic_vector(3 downto 0);
DATAIN: IN std_logic_vector(3 downto 0);
WRITEN: IN std_logic;
CLK: IN std_logic);
end test;
architecture inside of test is
component testram
port (A: IN std_logic_vector(5 downto 0);
DO: OUT std_logic_vector(3 downto 0);
DI: IN std_logic_vector(3 downto 0);
WR_EN: IN std_logic;
WR_CLK: IN std_logic);
end component;
begin
U0: testram port map(A=ADDRESS,DO=DATAOUT,DI=DATAIN,
WR_EN=WRITEN,WR_CLK=CLK);
end inside;
The following example shows a run script for instantiated LogiBLOX designs in VHDL code.
analyze -f vhdl “test.vhd” elaborate test
set_port_is_pad “*” insert_pads
compile
replace_fpga
ungroup -all -flatten
write_script test.dc
sh dc2ncf test.dc
write -f xnf -h -o “test.sxnf”
Instantiating RAM or ROM with FPGA Express
Use the following procedures and examples to instantiate a LogiBLOX RAM or ROM in Verilog or VHDL with FPGA Express.
- Create a LogiBLOX RAM or ROM with the LogiBLOX GUI.
When specifying options for LogiBLOX, specify the vendor type as Synopsys. Also specify in the LogiBLOX GUI whether you need Verilog or VHDL files.
- For Verilog, create an NGO, VEI, and V file. For VHDL, create an NGO, VHI, and VHD file.
The V and VHD files are simulation models. The VEI and VHI files are templates which assist in instantiating the LogiBLOX into your HDL. The NGO file is the actual LogiBLOX module for your design.
- For the Verilog flow, use the name of the NGO file as the name of the module instantiation in the Verilog code.
The VEI file contains the module name, pin names, and port names needed to instantiate the LogiBLOX memory. Do not rename the VEI file to a V file. Use the VEI file as a template for instantiating the LogiBLOX memory in your design.
- For the Verilog flow, make an empty Verilog file for the LogiBLOX module to tell the Synopsys netlist writer the pin directions for the LogiBLOX module.
- In the VEI file produced by LogiBLOX, there is a module with pin names and pin directions. Cut this empty module out and place it in a Verilog file with the same name as the LogiBLOX module you created.
Read this file into FPGA Express during the compile of your design.
- After implementing the design files in FPGA Express, notice in the Warnings window a number of warnings about the instantiated LogiBLOX module. FPGA Express reports that it cannot link to the instantiated design. Also, FPGA Express can report that some of the wires attached to the instantiated LogiBLOX have multiple drivers. Ignore these warnings.
Additionally, after implementing the design, in the modules view in the Edit Constraints view, all instantiated LogiBLOX modules are tagged as UNLINKED, a normal situation. UNLINKED means that FPGA Express cannot find a library cell in its synthesis library that matches, normal because the instantiated LogiBLOX is a black-box. See the “Results in FPGA Express after Implementing a Verilog Design with Instantiated LogiBLOX” figure and “Results in FPGA Express after Implementing a Verilog Design with Instantiated LogiBLOX (2)” figure.
- After implementing the design, if the implementation icon contains a “!” mark, optimize (synthesize) the design and write out the netlist file.
- For VHDL, use the name of the NGO file as the name of the component instantiation in the VHDL code.
The VHI file contains an example of how to instantiate the LogiBLOX into VHDL.
- After implementing the design files in FPGA Express, notice in the Warnings window a number of warnings about the instantiated LogiBLOX module. FPGA Express reports that it cannot link to the instantiated design. Also, FPGA Express can report that some of the wires attached to the instantiated LogiBLOX have multiple drivers. Ignore these warnings.
Additionally, after implementing the design, in the modules view in the Edit Constraints view, all instantiated LogiBLOX modules are tagged as UNLINKED, a normal situation. UNLINKED means that FPGA Express cannot find a library cell in its synthesis library that matches, normal because the instantiated LogiBLOX is a black-box. See the “Results in FPGA Express after Implementing a VHDL Design with Instantiated LogiBLOX” figure and “Results in FPGA Express after Implementing a VHDL Design with Instantiated LogiBLOX (2)” figure.
- After implementing the design, if the implementation icon contains a “!” mark, optimize (synthesize) the design and write out the netlist file.
The Verilog and VHDL examples that follow use a LogiBLOX synchronous RAM macro named “testmem.”
The following examples shows the testram LogiBLOX module V file created from the VEI file.
module testram(A, DO, DI, WR_EN, WR_CLK);
input [5:0] A;
output [3:0] DO;
input [3:0] DI;
input WR_EN;
input WR_CLK;
endmodule
The following example shows the instantiation of a LogiBLOX design in Verilog code.
module test(address,dataout,datain,writen,clk);
input [5:0] address;
output [3:0] dataout;
input [3:0] datain;
input writen;
input clk;
testram U0
( .A(address),
.DO(dataout),
.DI(datain),
.WR_EN(writen),
.WR_CLK(clk));
endmodule
The following examples shows an instantiation of a LogiBLOX design in VHDL code.
library IEEE;
use IEEE.std_logic_1164.all;
entity test is
port (ADDRESS: IN std_logic_vector(5 downto 0);
DATAOUT: OUT std_logic_vector(3 downto 0);
DATAIN: IN std_logic_vector(3 downto 0);
WRITEN: IN std_logic;
CLK: IN std_logic);
end test;
architecture inside of test is
component testram
port (A: IN std_logic_vector(5 downto 0);
DO: OUT std_logic_vector(3 downto 0);
DI: IN std_logic_vector(3 downto 0);
WR_EN: IN std_logic;
WR_CLK: IN std_logic);
end component;
begin
U0: testram port map(A=ADDRESS,DO=DATAOUT,DI=DATAIN,
WR_EN=WRITEN,WR_CLK=CLK);
end inside;
