Chapter 5

Simulating Your Design

You can efficiently manage your design changes with the XSI VHDL and Verilog simulation options described in this chapter. VHDL simulation supports the VHDL Initiative Towards ASIC Libraries (VITAL) standard, which allows you to simulate with any VITAL-compliant simulator, including Synopsys VSS. Built-in Verilog support allows you to simulate with Cadence Verilog-XL and other compatible simulators.

XSI simulation options provide the following.

• Fast, timing-accurate, gate-level HDL simulation with the VHDL, VITAL-compliant or Verilog versions of the SimPrim Library
  
  
• RTL or post-synthesis, functional verification of designs containing instantiated Xilinx Unified Library components, using either the VITAL or Verilog versions of the UNISIM Library
  
  
• Support for FPGA architecture features such as Global Set/Reset, Oscillator, RAM, and ROM
  
  

This chapter includes the following sections

• “Simulation Design Flow Overview” section
  
  
• “Using Simulation Libraries” section
  
  
• “Working with the VITAL Standard” section
  
  
• “VHDL and Verilog Simulation Flow” section
  
  
• “Synthesizing/Simulating for VHDL Global Set/Reset Emulation” section
  
  
• “NGDBuild Support of Multiple Device Architectures” section
  
  
• “Recommended VSS Simulation Strategy” section
  
  
• “VSS Simulation Flow” section
  
  
• “Editing the VSS Setup File” section
  
  
• “Creating a Testbench File” section
  
  
• “Using RTL Simulation” section
  
  
• “Implementing Your Design” section