HDL simulation can occur at five different steps in the design flow, as listed below. Subsequent sections describe each step in more detail.
The “VHDL and Verilog Simulation Flow” figure illustrates the design flow.
Figure 5.2 VHDL and Verilog Simulation Flow |  |
RTL simulation allows you to verify or simulate your HDL design at the system or chip level. High-level RTL language constructs usually describe the system or chip at this level. You can use VHDL and Verilog simulators to check your design's functionality before you implement it in gates.
Use a testbench to model the environment of the system or chip. At this level, you can use the UNISIM library to instantiate components from the Xilinx Unified Library. You can also instantiate LogiBLOX components if you do not want to use modules generated by your synthesis tool.
After synthesizing the system or chip to gates, re-use the testbench in post-synthesis, gate-level functional simulation to simulate the synthesized result. Check consistency with your original design description. In the Xilinx design flow, post-synthesis, gate-level simulation includes any simulation performed after any of the synthesis, map, or place and route steps.
A post-synthesis, pre-NGDBuild gate-level functional simulation allows you to directly verify your design after synthesis. Any differences in the behavior of the original RTL description and the synthesized design can indicate a problem with your synthesis tool. Not all synthesis tools support post-synthesis simulation. The synthesis tool must be able to write VHDL or Verilog output in terms of the UNISIM library.
LogiBLOX components remain behavioral models, expanded and represented as gates. The library usage guidelines for RTL simulation also apply to post-synthesis gate-level functional simulation.
If your synthesis tool cannot write UNISIM-compatible VHDL or Verilog netlists, you cannot simulate the synthesis output. In this case, use post-NGDBuild (pre-MAP) gate-level functional simulation with generic SimPrim library models. As with the post-synthesis, pre-NGDBuild simulation, this type of gate-level simulation allows you to verify that your design synthesized correctly.
In the Xilinx design flow, you can perform a partial timing simulation after your design maps (see the “VHDL and Verilog Simulation Flow” figure). The resulting NCD file contains timing information for the CLB and IOB mapped blocks. At this point your design is not routed and does not contain net delays, with the exception of pre-laid out macros such as cores.
After using PAR to route your design, you can simulate it with the actual block and net timing delays with the same testbench used in the earlier behavioral simulation. The back-annotation process produces a netlist of SimPrims annotated with the appropriate block and net delay data from the place and route process.
Different simulation libraries are required to support simulation before and after you run NGDBuild on your design. Prior to NGDBuild, designs are expressed as netlists containing Unified Library components. After NGDBuild, designs are expressed as netlists containing SimPrims. While the impact of these library changes are not apparent, designs need different simulation libraries for pre- and post-implementation simulation. Additionally, pre- and post-implementation netlists include different gate-level components.
