VITAL was created to promote the standardization of VHDL libraries and simulators from different vendors. VITAL also defines a standard for back-annotation of timing information to VHDL simulators.
The IEEE-STD 1076.4 VITAL standard accelerates gate-level simulations. Check with your simulator company to verify they support this standard. Also, make sure you use the proper settings and VHDL packages for this standard.
Your simulator can also accelerate IEEE-1164, the standard logic package for Types. VITAL libraries require overhead for timing checks and back-annotation styles. The UNISIM Library turns off these timing checks because they do not apply to unit delay functional simulation. The SimPrim back-annotation library by default turns on these timing checks. However, you can turn them off and then edit and re-compile the SimPrim components file.
